Michael Jason Wyatt

US Patent:

7400193, Jul 15, 2008

Filed:

Aug 15, 2006

Appl. No.:

11/504425

Inventors:

Michael A. Wyatt - Clearwater FL, US

Assignee:

ITT Manufacturing Enterprises, Inc. - Wilmington DE

International Classification:

H03F 3/00

US Classification:

330148, 330302, 330295, 330124 R

Abstract:

A wideband splitter includes a core amplifier for receiving a single pair of differential input signals and providing first and second pairs of differential output signals. The first pair of differential output signals and the second pair of differential outputs have substantially identical characteristics. A signal gain is implemented between the received single pair of differential input signals and the first and second pair of differential output signals. The signal gain is substantially constant across the frequency bandwidth of the core amplifier. A bandwidth peaking network is coupled to the core amplifier and includes (a) a first coil and a first resistor connected in series and (b) a second coil and a second resistor connected in series. The bandwidth peaking network is configured to increase the frequency bandwidth of the core amplifier.

US Patent:

7400196, Jul 15, 2008

Filed:

Aug 15, 2006

Appl. No.:

11/504431

Inventors:

Michael A. Wyatt - Clearwater FL, US

Assignee:

ITT Manufacturing Enterprises, Inc. - Wilmington DE

International Classification:

H03F 3/18

US Classification:

330263, 330302, 330258, 330311

Abstract:

A wide band amplifier includes a core amplifier having input terminals and output terminals for, respectively, receiving differential input signals and providing amplified differential output signals. A bandwidth peaking network is coupled to the core amplifier and includes (a) a first coil and a first resistor connected in series and (b) a second coil and a second resistor connected in series. The first coil and resistor and the second coil and resistor, respectively, are coupled to the core amplifier for receiving the amplified differential output signals. The bandwidth peaking network is configured to increase the frequency bandwidth of the amplifier. The bandwidth peaking network includes (a) a first node formed between the first coil and resistor, (b) a second node formed between the second coil and resistor, and (c) a third resistor is connected between the first node and the second node. This resistor is free of current flow at low frequency operation of the amplifier.

US Patent:

7504879, Mar 17, 2009

Filed:

Aug 24, 2006

Appl. No.:

11/510443

Inventors:

Michael Wyatt - Clearwater FL, US

Assignee:

ITT Manufacturing Enterprises, Inc. - Wilmington DE

International Classification:

G05F 1/00

US Classification:

327552, 327558

Abstract:

A transconductor and filter circuit is described. In one embodiment, a front end module within the transconductor and filter circuit converts a differential input voltage signal into a differential output current and supplies the output current at a differential output. A filter module coupled to the differential output of the front end module receives the differential output current, converts the output current into an intermediary differential voltage, and filters the differential voltage to obtain a filtered differential output voltage signal having low output impedance.

US Patent:

7587187, Sep 8, 2009

Filed:

Aug 15, 2006

Appl. No.:

11/504426

Inventors:

Michael A. Wyatt - Clearwater FL, US

Assignee:

ITT Manufacturing Enterprises, Inc. - Wilmington DE

International Classification:

H04B 1/06

US Classification:

4552321, 455296, 455313, 455323, 455333

Abstract:

A wideband mixer includes a core mixer having input terminals and output terminals for, respectively, receiving differential input signals and providing amplified differential output signals. A steering module is coupled to the core mixer for receiving differential reference signals and providing bi-phase modulated amplified differential output signals. The core mixer is configured to provide a value of gain between the differential input signals and the differential output signals. A bandwidth peaking network is coupled to the core mixer and includes (a) a first coil and a first resistor connected in series and (b) a second coil and a second resistor connected in series. The first coil and resistor and the second coil and resistor, respectively, are coupled to the core mixer for receiving the amplified differential output signals. The bandwidth peaking network is configured to increase the frequency bandwidth of the core mixer.

US Patent:

7598773, Oct 6, 2009

Filed:

Oct 29, 2007

Appl. No.:

11/926622

Inventors:

Michael A. Wyatt - Clearwater FL, US

Assignee:

ITT Manufacturing Enterprises, Inc. - Wilmington DE

International Classification:

H03K 19/007
H03K 19/00

US Classification:

326109, 326 23, 326 83, 326 84

Abstract:

A radiation hardened inverter includes first and second electrical paths between an input terminal and an output terminal. A first PFET is disposed in the first electrical path, and a bipolar junction transistor (BJT) is disposed in the second electrical path. The first PFET is configured to convert a low level signal at the input terminal to a high level signal at the output terminal, and the BJT is configured to convert a high level signal at the input terminal to a low level signal at the output terminal. The radiation hardened inverter includes a second PFET disposed in the second electrical path. The second PFET is configured to provide a path for bleeding excess current away from the BJT. The radiation hardened inverter also includes a current limiting PFET disposed in the second electrical path. The current limiting PFET is configured to limit current flowing into a base of the BJT.

US Patent:

7668522, Feb 23, 2010

Filed:

Aug 15, 2006

Appl. No.:

11/504430

Inventors:

Michael A. Wyatt - Clearwater FL, US

Assignee:

ITT Manufacturing Enterprises, Inc. - Wilmington DE

International Classification:

H04B 1/16

US Classification:

4552321, 455137, 455296, 455313, 455323, 455333

Abstract:

A wideband combiner includes a core amplifier for receiving first and second pairs of differential input signals and providing a single pair of differential output signals. The pair of differential output signals are a combination of the first and second pair of differential input signals and a signal gain is implemented between the received first and second pairs of differential input signals and the single pair of differential output signals. The core amplifier is configured to provide a gain value between the first and second pairs of differential input signals and the single pair of differential output signals. The signal gain is substantially constant across the frequency bandwidth of the core amplifier. A bandwidth peaking network is coupled to the core amplifier and includes (a) a first coil and a first resistor connected in series and (b) a second coil and a second resistor connected in series.

US Patent:

7728565, Jun 1, 2010

Filed:

Nov 12, 2007

Appl. No.:

11/938354

Inventors:

Michael A. Wyatt - Clearwater FL, US

Assignee:

ITT Manufacturing Enterprises, Inc. - Wilmington DE

International Classification:

G05F 1/613
G05F 1/575

US Classification:

323269, 323273

Abstract:

A low dropout (LDO) voltage regulator includes an output terminal for providing a regulated voltage output to a load, and a plurality of PFETs connected in parallel. Each PFET drains a level of current and the sum of the levels of current are provided as a current output at the output terminal. The LDO voltage regulator also includes a feedback network coupled to the output terminal for providing a voltage feedback signal, and an error amplifier coupled between the plurality of PFETs and the feedback network for sensing a differential voltage. The error amplifier includes an output voltage which is provided to the plurality of PFETs for adjusting the drain of current from each PFET. A summation of the drains of current from each PFET is provided as the current output to regulate the voltage output at the output terminal. Each PFET drains a current level of Iand the summation of the drains of current is the current output I.

US Patent:

7812677, Oct 12, 2010

Filed:

Nov 30, 2007

Appl. No.:

11/947954

Inventors:

Michael Anthony Wyatt - Clearwater FL, US

Assignee:

ITT Manufacturing Enterprises, Inc. - Wilmington DE

International Classification:

H03L 7/00

US Classification:

331 17, 331 16, 331 34, 331177 R

Abstract:

A frequency synthesizer includes a phase locked loop (PLL) for generating a desired frequency. The PLL includes two loop filters. A characterization circuit is included, which is configured to receive a digital word for characterizing the PLL and provide a pre-charge value for pre-charging one of the loop filters to generate the desired frequency. A successive approximation analog to digital (A/D) converter is coupled between the loop filters and the characterization circuit, for providing both (a) the digital word to the characterization circuit, and (b) the pre-charge value to the selected loop filter. The digital word includes n-bits ranging in values from a most significant bit (MSB) to a least significant bit (LSB), and the pre-charge value is formed by the n-bits. The successive approximation A/D converter includes a successive approximation register (SAR) for forming the digital word, and a digital to analog (D/A) converter for forming the pre-charge value. The successive approximation A/D converter includes a comparator for comparing (a) a value corresponding to a loop filter voltage with (b) an analog value formed by a bit of the digital word.