Michael Jin-Kai Yang

US Patent:

8123881, Feb 28, 2012

Filed:

Oct 9, 2008

Appl. No.:

12/248204

Inventors:

Damon K. Cox - Round Rock TX, US
Todd J. Egan - Fremont CA, US
Michael X. Yang - Palo Alto CA, US
Jeffrey C. Hudgens - San Francisco CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

B32B 37/00

US Classification:

156 64, 29721, 29739, 29740, 438107, 438108

Abstract:

A method, a system and a computer readable medium having a set of instructions stored thereon for die-to-robot alignment for die-to-substrate bonding are described. First, a robot is aligned with a substrate to provide a pre-aligned robot. Next, a die is aligned with the pre-aligned robot to provide a robot-aligned die. Finally, the robot-aligned die is bonded to a region of the substrate. The substrate is held stationary immediately following the aligning of the robot with the substrate and at least until the robot-aligned die is bonded to the region of the substrate.

US Patent:

20090130821, May 21, 2009

Filed:

Oct 10, 2008

Appl. No.:

12/249812

Inventors:

Damon K. Cox - Round Rock TX, US
Todd J. Egan - Fremont CA, US
Michael X. Yang - Palo Alto CA, US
Jeffrey C. Hudgens - San Francisco CA, US
Ingrid B. Peterson - Menlo Park CA, US
Michael R. Rice - Pleasanton CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 21/30
G06F 17/50

US Classification:

438455, 716 2, 156538, 1563798, 257E21598

Abstract:

A method, a system and a computer readable medium for three dimensional packaging with wafer-level bonding and chip-level repair. A first wafer is provided having a first plurality of chips. A second wafer is provided having a second plurality of chips. At least one chip is removed from the second wafer while retaining the relative alignment of the remaining chips in the second wafer. The first and second wafers are aligned and joined with wafer-to-wafer techniques. Where a bad chip having a relative physical position within the second wafer corresponding to a relative physical position within the first wafer of a good chip is removed, a good chip may be aligned and bonded to the first wafer using die-to-wafer techniques.