Minesh C Patel

US Patent:

6576522, Jun 10, 2003

Filed:

Dec 8, 2000

Appl. No.:

09/733570

Inventors:

Sundar Srinivasan Chetlur - Singapore, SG
Pradip Kumar Roy - Orlando FL
Minesh Amrat Patel - Orlando FL
Sidhartha Sen - Singapore, SG
Vivek Saxena - Orlando FL

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H01L 21336

US Classification:

438359, 438660, 438795

Abstract:

A method for deuterium sintering to improve the hot carrier aging of an integrated circuit includes (a) providing a partially fabricated integrated circuit structure comprising a semiconductor substrate and a dielectric layer formed on at least a portion of the substrate, the dielectric layer having at least one conductive material via plug formed therein and (b) sintering the structure in the presence of a gas comprising deuterium-containing components at high temperatures prior to a metallization layer being deposited on the structure.

US Patent:

6605529, Aug 12, 2003

Filed:

May 11, 2001

Appl. No.:

09/853317

Inventors:

Sundar Chetlur - Singapore, SG
Jennifer M. McKinley - Orlando FL
Minesh A. Patel - Orlando FL
Pradip K. Roy - Orlando FL
Jonathan Zhong-Ning Zhou - Orlando FL

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H01L 214763

US Classification:

438627, 438585, 438643, 438795

Abstract:

The present invention provides a method of manufacturing a semiconductor device that includes incorporation of a hydrogen isotope at a relatively high processing temperature during gate oxidation or polysilicon gate electrode deposition to maximize incorporation of hydrogen isotope at interfaces deliberately created during oxidation (such as graded oxidation) as multilayered poly/alpha-silicon deposition process.

US Patent:

6940151, Sep 6, 2005

Filed:

Sep 30, 2002

Appl. No.:

10/261463

Inventors:

Michael Scott Carroll - Orlando FL, US
Yi Ma - Santa Clara CA, US
Minesh Amrat Patel - Orlando FL, US
Peyman Sana - Orlando FL, US

Assignee:

Agere Systems, Inc. - Allentown PA

International Classification:

H01L031/0392

US Classification:

257649, 257636, 257630, 257640

Abstract:

A low-thermal budget, silicon-rich silicon nitride film may include a concentration of hydrogen in Si—H bonds being at least 1. 5 times as great as a concentration of hydrogen in N—H bonds. The silicon nitride film suppresses boron diffusion in boron-doped devices when such devices are processed using high-temperature processing operations that conventionally urge boron diffusion. The low-thermal budget, silicon-rich silicon nitride film may be used to form spacers in CMOS devices, it may be used as part of a dielectric stack to prevent shorting in tightly packed SRAM arrays, and it may be used in BiCMOS processing to form a base nitride layer and/or nitride spacers isolating the base from the emitter. Furthermore the low-thermal budget, silicon-rich silicon nitride film may remain covering the CMOS structure while bipolar devices are being formed, as it suppresses the boron diffusion that results in boron penetration and boron-doped poly depletion.

US Patent:

6391668, May 21, 2002

Filed:

May 1, 2000

Appl. No.:

09/562346

Inventors:

Carlos M. Chacon - Orlando FL
Sundar S. Chetlur - Orlando FL
Brian E. Harding - Orlando FL
Minesh A. Patel - Orlando FL
Pradip K. Roy - Orlando FL

Assignee:

Agere Systems Guardian Corp. - Orlando FL

International Classification:

H01L 2166

US Classification:

438 17, 438197, 324769

Abstract:

The present invention provides a method of determining a trap density of a semiconductor substrate/dielectric interface. In one embodiment, the method comprises measuring a current within a semiconductor substrate resulting from a flow of carriers from traps located near the interface, wherein the measured current is a function of the number of traps located at the interface, and determining the trap density as a function of the measured current.