Ming Jen Chen

US Patent:

6700548, Mar 2, 2004

Filed:

Sep 27, 2002

Appl. No.:

10/256663

Inventors:

Ming Hui Chen - Rancho Palos Verdes CA
Rong Chan Hsieh - Taipei, TW
Wei Tse Cheng - Tainan Hsien, TW

Assignee:

Victory Industrial Corporation - Taipei Hsine

International Classification:

H01Q 1310

US Classification:

343771, 343772, 343786, 333135

Abstract:

A dual band antenna feed is made with an embedded waveguide structure to enable combining of Ka and Ku band signals without the need for an additional cavity-type filter. The antenna feed includes a Ka and Ku band interface section ( ) with two Ka band vertical polarization waveguide sections ( ) and ( ), and a single Ku band waveguide section ( ) which carries both vertical and horizontal polarization Ku band signals. The opposing walls ( ) of the Ku band waveguide ( ) carrying the vertical polarization Ku band signals are transitioned to step down from an input section ( ) to successively smaller dimensioned sections ( ), and then to step back up in successively larger dimensioned sections ( ) to an output section ( ). The two Ka band sections ( ) are fed into openings in Ku band section. ( ), on opposite sides of the opening for the Ku band transition section ( ).

US Patent:

6842085, Jan 11, 2005

Filed:

Feb 18, 2003

Appl. No.:

10/248777

Inventors:

Ming H. Chen - Rancho Palos Verdes CA, US
Chin-Yi Chu - Hsi Chih, TW

Assignee:

Victory Microwave Corporation - Hsi Chih City

International Classification:

H01P 512

US Classification:

333125, 333 21 A, 333122, 333135

Abstract:

An orthomode transducer includes a first waveguide section, a second waveguide section coupled to the first waveguide section, and a third waveguide section coupled to the first and second waveguide sections. The first waveguide section is configured to support the propagation of a signal having a first polarization, and includes a first waveguide aperture sized to communicate the signal having the first polarization therethrough. The second waveguide is configured to support the propagation of a signal having a second polarization which is orthogonal to the first polarization, the second waveguide section having a single internal septum and a second waveguide aperture sized to communicate the signal having the second polarization therethrough. The third waveguide is configured to support the propagation of either a signal having the first polarization or the second polarization, and includes a third waveguide aperture sized to communicate the signals having either the first or second polarization therethrough.

US Patent:

6915335, Jul 5, 2005

Filed:

Sep 17, 2001

Appl. No.:

09/955004

Inventors:

Ming Chi Chen - Union City CA, US
Robert Chen - Fremont CA, US
Sanjoy Dey - Fremont CA, US
James Everett Grishaw - Santa Clara CA, US
Mick Henniger - Buchanan Dam TX, US

Assignee:

Cisco Technology, Inc. - San Jose CA

International Classification:

G06F015/16

US Classification:

709213, 709250, 709229, 710 8, 710 10, 710 11, 710 15

Abstract:

A method and apparatus for implementing host management of an intelligent daughtercard utilizes a high-speed serial link and a defined plurality of serial protocol commands to provide high bandwidth control path for management of daughtercard memory and application specific initialization and/or configuration changes.

US Patent:

6950355, Sep 27, 2005

Filed:

Dec 18, 2001

Appl. No.:

10/020208

Inventors:

Surya Battacharya - Irvine CA, US
Ming Chen - Mission Viejo CA, US
Liming Tsau - Irvine CA, US
Henry Chen - Irvine CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

G11C007/00

US Classification:

365201, 365154

Abstract:

A method for testing a semiconductor wafer. An array of probes is coupled to the semiconductor wafer. Then a voltage difference is applied across a plurality of adjacent metal line pairs (e. g. , wordline and/or bitline pairs) of one or more SRAM arrays of at least one die. Application of the voltage difference induces failure of metal stringers or defects between the adjacent lines. Additionally, the voltage can be applied across respective pairs of substantially all parallel metal lines of the one or more SRAM arrays of more that one die of the semiconductor wafer.

US Patent:

6999039, Feb 14, 2006

Filed:

Sep 18, 2004

Appl. No.:

10/943533

Inventors:

Ming Hui Chen - Rancho Palos Verdes CA, US

Assignee:

Victory Microwave Corporation - Hsi Chih

International Classification:

H01Q 13/10

US Classification:

343771

Abstract:

A method for manufacturing an extruded slot antenna array includes extruding a slot antenna body, the slot antenna including a first major surface, a second major surface, first and second external side walls, and one or more longitudinally extending internal waveguide walls disposed between the first and second major surfaces. Each of the internal waveguide walls forms a respective two or more open-ended waveguides, each open-ended waveguide having a first open end and a second open end. An array of slots is cut on the first major surface of the slot antenna body, the array of slots being arranged in a plurality of rows, one row of slots being formed along a longitudinal line of a respective open-ended waveguide. Next, a row of slots are subsequently cut on the second major surface of the extruded slot antenna body, the row of slots formed substantially perpendicularly to the longitudinal axis of the open-ended waveguides, one of the slots being formed on each of the open-ended waveguides. Next, end caps are attached to the first and second open-ends of each of the open-ended waveguides.

US Patent:

7108559, Sep 19, 2006

Filed:

Dec 21, 2004

Appl. No.:

11/020733

Inventors:

Helen Shtargot - Foster City CA, US
Dattatri Mattur - Sunnyvale CA, US
Shawn Bender - Campbell CA, US
William J. Lewis - Mountain View CA, US
Lwin Tint - Newark CA, US
David Tarkington - Sunnyvale CA, US
Ming Chi Chen - Union City CA, US
Rene Duzac - San Jose CA, US
James Everett Grishaw - Santa Clara CA, US
Torence Lu - Fremont CA, US
Kimberly Rae Turner - Apex NC, US
Phong Hoang Ho - Cary NC, US
Robert A. Loose - Cary NC, US
Stephen Scearce - Apex NC, US

Assignee:

Cisco Technology, INc. - San Jose CA

International Classification:

H01R 25/00
H01R 12/00
H01R 27/02
H01R 31/00
H05K 1/00

US Classification:

439638, 439 69

Abstract:

A router includes WIC and Network Module slots that be reconfigured to hold cards and network modules having different form factors. A motherboard/midplane arrangement provides for a field replaceable motherboard that can be replaced without removing the router from the rack.

US Patent:

7285022, Oct 23, 2007

Filed:

Sep 18, 2006

Appl. No.:

11/523320

Inventors:

Helen Shtargot - Foster City CA, US
Shawn Bender - Campbell CA, US
William J. Lewis - Mountain View CA, US
Lwin Tint - Newark CA, US
David Tarkington - Sunnyvale CA, US
Ming Chi Chen - Union City CA, US
Rene Duzac - San Jose CA, US
James Everett Grishaw - Santa Clara CA, US
Torence Lu - Fremont CA, US
Kimberly Rae Turner - Dublin OH, US
Phong Hoang Ho - Cary NC, US
Robert A. Loose - Cary NC, US
Stephen Scearce - Apex NC, US
Terri Cruse - Lathrop CA, US

Assignee:

Cisco Technology, Inc. - San Jose CA

International Classification:

H01R 25/00

US Classification:

439638

Abstract:

A network device includes card slots and Network Module slots that be reconfigured to hold cards and network modules having different form factors.

US Patent:

7333106, Feb 19, 2008

Filed:

Mar 27, 2003

Appl. No.:

10/402304

Inventors:

Tsailai Terry Wu - San Jose CA, US
Ming Chen - San Jose CA, US

Assignee:

Silicon Motion, Inc. - Milpitas CA

International Classification:

G06T 15/40

US Classification:

345422, 345421, 345531, 345532, 345536, 345542, 345559

Abstract:

In one embodiment, the invention is an apparatus. The apparatus includes a Z-buffer memory. The apparatus also includes a set of bits, each of which corresponds to a block of the Z-buffer memory. The apparatus also includes an initialization (init) register. The apparatus also includes control logic coupled to the Z-buffer memory, the set of bits, and the init register. The control logic sets the set of bits upon receipt of an initialization request. The control logic retrieves a Z value from either the init register or from the Z-buffer memory according to the states of the set of bits.