Mingtao Li

US Patent:

7696101, Apr 13, 2010

Filed:

Nov 1, 2005

Appl. No.:

11/263885

Inventors:

Mingtao Li - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 21/302
H01L 21/461

US Classification:

438736, 257E21035, 257E21038, 438947

Abstract:

A method used during the manufacture of a semiconductor device comprises the formation of a first patterned layer having individual features of a first density. Through the formation and etching of various layers, for example conformal layers and a spun-on layer, a second patterned layer results which comprises individual features of a second density, which is about three times the first density. An in-process semiconductor apparatus formed using the method, and a system comprising the semiconductor apparatus formed according to the method, is also described.

US Patent:

7717696, May 18, 2010

Filed:

Aug 13, 2004

Appl. No.:

10/918564

Inventors:

Stephen Chou - Princeton NJ, US
Linshu Kong - Plainsboro NJ, US
Colby Steere - Parsippany NJ, US
Mingtao (Gary) Li - Boise ID, US
Hua Tan - South Bound Brook NJ, US
Lin Hu - Livingston NJ, US

Assignee:

Nanonex Corp. - Princeton NJ

International Classification:

B29C 59/00

US Classification:

425400, 425385, 4253871, 425394, 425419, 425468, 425470, 425810, 101485, 216 44, 216 52, 264293

Abstract:

Apparatus for double-sided imprint lithography of an apertured substrate comprises a pair of correspondingly apertured molds, a support for an assembly of the substrate and molds, and an alignment mechanism with radially movable elements for aligning the apertures of the molds and the substrate. The movable elements can be at least partially disposed in a spindle and can be removed radially outward by a conically tapered drive rod. Opposing surfaces of the substrate can then be imprinted in registration at the same time, preferably by fluid pressure imprint lithography.

US Patent:

7935639, May 3, 2011

Filed:

Apr 9, 2010

Appl. No.:

12/757898

Inventors:

Mingtao Li - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 21/461

US Classification:

438736, 438694, 438725, 438947, 257E21035, 257E21038

Abstract:

Methods used during the manufacture of a semiconductor device, such as one that includes forming a plurality of vertically oriented first support features. Each feature comprises first and second sidewalls and the first support features are formed to have a first pitch. A plurality of first mask spacers are formed, wherein one first mask spacer is formed on each first support feature sidewall, and each first mask spacer comprises an exposed, vertically oriented sidewall. A plurality of vertically oriented second support features are formed, wherein one second support feature is formed on the exposed, vertically oriented sidewall of each first mask spacer, and each second support feature is separated from an adjacent second support feature by a gap. A plurality of second mask features are formed, wherein one second mask feature is formed within each gap. The first and second support features are removed, and the first and second mask spacers are left to provide an etch pattern, wherein the first and second mask features have a second pitch.

US Patent:

20050145119, Jul 7, 2005

Filed:

Aug 25, 2004

Appl. No.:

10/926376

Inventors:

Hua Tan - South Bound Brook NJ, US
Linshu Kong - Plainsboro NJ, US
Mingtao Li - Boise ID, US
Stephen Chou - Princeton NJ, US

International Classification:

B31F001/07

US Classification:

101003100

Abstract:

Improved apparatus for imprint lithography involves using direct fluid pressure to press a mold into a substrate-supported film. Advantageously the mold and/or substrate are sufficiently flexible to provide wide area contact under the fluid pressure. Fluid pressing can be accomplished by sealing the mold against the film and disposing the resulting assembly in a pressurized chamber. The result of this fluid pressing is enhanced resolution and high uniformity over an enlarged area.

US Patent:

20130093050, Apr 18, 2013

Filed:

Oct 18, 2011

Appl. No.:

13/276125

Inventors:

Brett W. Busch - Boise ID, US
Mingtao Li - Boise ID, US
Jennifer Lequn Liu - Boise ID, US
Kevin R. Shea - Boise ID, US
Belford T. Coursey - Boise ID, US
Jonathan T. Doebler - Boise ID, US

Assignee:

MICRON TECHNOLOGY, INC. - Boise ID

International Classification:

H01L 29/92
H01L 21/02

US Classification:

257532, 438381, 257E21008, 257E29342

Abstract:

A method of forming capacitors includes providing a support material over a substrate. The support material is at least one of semiconductive or conductive. Openings are formed into the support material. The openings include at least one of semiconductive or conductive sidewalls. An insulator is deposited along the semiconductive and/or conductive opening sidewalls. A pair of capacitor electrodes having capacitor dielectric there-between is formed within the respective openings laterally inward of the deposited insulator. One of the pair of capacitor electrodes within the respective openings is laterally adjacent the deposited insulator. Other aspects are disclosed, including integrated circuitry independent of method of manufacture.

US Patent:

20160027863, Jan 28, 2016

Filed:

Jul 2, 2015

Appl. No.:

14/791114

Inventors:

- Boise ID, US
Mingtao Li - Boise ID, US
Lequn Jennifer Liu - Boise ID, US
Kevin R. Shea - Boise ID, US
Belford T. Coursey - Boise ID, US
Jonathan T. Doebler - Boise ID, US

Assignee:

MICRON TECHNOLOGY, INC. - Boise ID

International Classification:

H01L 49/02
H01L 23/525

Abstract:

A method of forming capacitors includes providing a support material over a substrate. The support material is at least one of semiconductive or conductive. Openings are formed into the support material. The openings include at least one of semiconductive or conductive sidewalls. An insulator is deposited along the semiconductive and/or conductive opening sidewalls. A pair of capacitor electrodes having capacitor dielectric there-between is formed within the respective openings laterally inward of the deposited insulator. One of the pair of capacitor electrodes within the respective openings is laterally adjacent the deposited insulator. Other aspects are disclosed, including integrated circuitry independent of method of manufacture.

US Patent:

20150194430, Jul 9, 2015

Filed:

Jan 6, 2014

Appl. No.:

14/148402

Inventors:

- Boise ID, US
Mingtao Li - Boise ID, US
Haitao Liu - Boise ID, US
Deepak Chandra Pandey - Boise ID, US
Mark Fischer - Meridian ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 27/108
H01L 29/66
H01L 27/105

Abstract:

A semiconductor device comprises a recessed access device that includes a first pillar, a second pillar, a channel region connecting the first and second pillars, and a gate disposed over the channel region. The channel region has a width that is narrower than widths of the first pillar and the second pillar. An array of recessed access devices comprises a plurality of pillars protruding from a substrate, and a plurality of channel regions. Each channel region has a width that is less than about 10 nm and couples neighboring pillars to form a plurality of junctionless recessed access devices. A method of forming at least one recessed access device also comprises forming pillars over a substrate, forming at least a channel region coupled with the pillars, the channel region having a relatively narrow width, and forming a gate at least partially surrounding the channel region on at least three sides.