Minh Cong Le

US Patent:

7099202, Aug 29, 2006

Filed:

Apr 8, 2005

Appl. No.:

11/102906

Inventors:

Jinshu Son - Saratoga CA, US
Liqi Wang - Mt. View CA, US
Minh V. Le - Richmond CA, US
Philip S. Ng - Cupertino CA, US

Assignee:

Atmel Corporation - San Jose CA

International Classification:

G11C 11/34

US Classification:

36518905, 36518902

Abstract:

A multiplexer circuit in a memory organized into page-portions has a plurality of bit-select multiplexers configured to couple a plurality of page-portion global bitlines to a sense amplifier input. A plurality of column address lines organized into data bytes comprises each page-portion. A plurality of column multiplexers couple the data bytes to the page-portion global bitlines such that each of the address lines comprising the data byte is coupled to one of the page-portion global bitlines.

US Patent:

7102950, Sep 5, 2006

Filed:

Aug 2, 2004

Appl. No.:

10/910038

Inventors:

Jinshu Son - Saratoga CA, US
Liqi Wang - Mountain View CA, US
Minh V. Le - Richmond CA, US
Philip S. Ng - Cupertino CA, US

Assignee:

Atmel Corporation - San Jose CA

International Classification:

G11C 7/00

US Classification:

3652257, 36518904

Abstract:

Fuse data used to configure ancillary circuits used with a non-volatile serial memory core are stored in locations within the memory core. As a first opcode or word is sent on a serial bus to the memory, a logic circuit intercepts the word and generates read fuse enable pulses that fetch the fuse data and configure the ancillary circuits before the last bit of the first command byte arrives. If a read operation is designated, the memory circuits are configured to read. If a write operation is designated, further fuse data is fetched from the memory core to configure ancillary circuits for writing. The fuse data is written to the memory core at the time of circuit manufacture thereby obviating the need for separate storage locations.

US Patent:

7257046, Aug 14, 2007

Filed:

Jun 13, 2005

Appl. No.:

11/151332

Inventors:

Jinshu Son - Saratoga CA, US
Liqi Wang - Mt. View CA, US
Minh V. Le - Richmond CA, US
Philip S. Ng - Cupertino CA, US

Assignee:

Atmel Corporation - San Jose CA

International Classification:

G11C 8/10

US Classification:

36523003, 36523006, 3652385

Abstract:

A bitline selection network is composed of a plurality of bitlines and a plurality of global bitlines. The bitlines are grouped into bytes with eight bitlines per byte. The bitlines provide access to memory cells for read and write operations. A bitline is connected to a global bitline through a bitline select transistor. Each of the bitline select transistors is activated one at a time by a bitline select controller. Activation of each bitline select transistor provides a connection to a source line, which in turn connects to a sense amplifier and a write data loading logic block. The sense amplifier and the write data loading logic block are used in read and write operations respectively.

US Patent:

7336540, Feb 26, 2008

Filed:

Mar 29, 2006

Appl. No.:

11/393551

Inventors:

Philip S. Ng - Cupertino CA, US
Minh V. Le - Stockton CA, US
Liqi Wang - Sunnyvale CA, US
Jinshu Son - Saratoga CA, US

Assignee:

Atmel Corporation - San Jose CA

International Classification:

G11C 11/34

US Classification:

3651852, 36518523, 36518524

Abstract:

An electronic test structure and method for testing non-volatile memory cells. The structure includes a first transistor coupled in series to a floating gate transistor whereby a source of the first transistor is coupled to a positive power supply voltage and a source of the floating gate transistor is coupled to a power supply ground. A gate of the first transistor is further coupled to a source of the first transistor. A second transistor is coupled in series with a memory cell with a source of the second transistor coupled to a positive power supply voltage and a gate of the second transistor is coupled to the drain of the first transistor.

US Patent:

7751248, Jul 6, 2010

Filed:

Feb 26, 2008

Appl. No.:

12/037880

Inventors:

Philip S. Ng - Cupertino CA, US
Minh V. Le - Stockton CA, US
Liqi Wang - Sunnyvale CA, US
Jinshu Son - Saratoga CA, US

Assignee:

Atmel Corporation - San Jose CA

International Classification:

G11C 11/34

US Classification:

3651852, 36518523, 36518524

Abstract:

An electronic test structure and method for testing non-volatile memory cells. The structure includes a first transistor coupled in series to a floating gate transistor whereby a source of the first transistor is coupled to a positive power supply voltage and a source of the floating gate transistor is coupled to a power supply ground. A gate of the first transistor is further coupled to a source of the first transistor. A second transistor is coupled in series with a memory cell with a source of the second transistor coupled to a positive power supply voltage and a gate of the second transistor is coupled to the drain of the first transistor.

US Patent:

8394659, Mar 12, 2013

Filed:

Sep 21, 2012

Appl. No.:

13/624406

Inventors:

Guowen Ding - San Jose CA, US
Minh Huu Le - San Jose CA, US
Guizhen Zhang - Santa Clara CA, US

Assignee:

Intermolecular, Inc. - San Jose CA

International Classification:

H01L 21/00

US Classification:

438 57, 136244, 136252, 136262, 136265, 257E21068, 438 93, 438 95

Abstract:

Methods for forming Cu—In—Ga—N (CIGN) layers for use in TFPV solar panels are described using reactive PVD deposition in a nitrogen containing atmosphere. In some embodiments, the CIGN layers can be used as an absorber layer and eliminate the need of a selenization step. In some embodiments, the CIGN layers can be used as a protective layer to decrease the sensitivity of the CIG layer to oxygen or moisture before the selenization step. In some embodiments, the CIGN layers can be used as an adhesion layer to improve the adhesion between the back contact layer and the absorber layer.

US Patent:

8412479, Apr 2, 2013

Filed:

Jun 29, 2010

Appl. No.:

12/826039

Inventors:

Howard S. David - Portland OR, US
Eugene Gorbatov - Hillsboro OR, US
Ulf R. Hanebutte - Gig Harbor WA, US
Minh Le - North Plains OR, US
Rahul Khanna - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 19/00

US Classification:

702 85, 702107, 702126, 702189, 323281, 323293, 323303, 363 95, 363 97, 365227

Abstract:

Memory power estimation by means of calibrated weights and activity counters are generally presented. In this regard, in one embodiment, a memory power is introduced to read a value from a memory activity counter, to determine a memory power estimation based at least in part on the value and a calibration, and to store the memory power estimation to a register. Other embodiments are also described and claimed.

US Patent:

8619528, Dec 31, 2013

Filed:

Aug 31, 2011

Appl. No.:

13/223199

Inventors:

Hamid Ghazvini - San Jose CA, US
David Kuo - Palo Alto CA, US
Minh Huong Le - San Jose CA, US
Kim Yang Lee - Fremont CA, US
HongYing Wang - Fremont CA, US
Nobuo Kurataka - Campbell CA, US
Yautzong Hsu - Fremont CA, US
Henry Hung Yang - San Jose CA, US

Assignee:

Seagate Technology LLC - Cupertino CA

International Classification:

G11B 20/00

US Classification:

369 531, 369 4426, 3562373, 264293

Abstract:

A system and method of calibrating optical measuring equipment includes optically measuring discrete objects of a first known predictable pattern from a calibration apparatus, wherein the first known predictable pattern is a bit pattern. A recording surface optical reader is calibrated based on the optically measuring. Using the first known predictable pattern, contamination is filtered from the results of the optically measuring.