Mohammad M Negahban

US Patent:

7836379, Nov 16, 2010

Filed:

Nov 29, 2006

Appl. No.:

11/605797

Inventors:

Paul B. Ricci - Rancho Santa Margarita CA, US
Mohammad M. Negahban - Coto de Caza CA, US
Yujun Si - Tustin CA, US

Assignee:

Marvell International Ltd. - Hamilton

International Classification:

G11C 29/00
H03M 13/00

US Classification:

714770, 714769, 714755

Abstract:

A system includes a receive module, a control module and a read module. The receive module receives a first block that includes first data, a first cyclic redundancy check (CRC) checksum, and a first error-correcting code (ECC) value. The first CRC checksum and the first ECC value include a logical block address (LBA). The control module generates a first derived CRC checksum based on the first data. The first derived CRC checksum does not include the LBA. The read module reads a second block from a parity disk. The second block includes parity data, a second CRC checksum, and a second ECC value. The second CRC checksum and the second ECC value include the LBA.