Moon S Kim

US Patent:

8438404, May 7, 2013

Filed:

Sep 30, 2008

Appl. No.:

12/241332

Inventors:

Karl J. Duvalsaint - Lagrangevillle NY, US
Harm P. Hofstee - Austin TX, US
Daeik Kim - Beacon NY, US
Moon J. Kim - Wappingers Falls NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 13/00
G06F 7/04
G06F 15/173
G06F 9/45
G06F 15/00
G06F 9/46
H04L 12/28

US Classification:

713300, 712 30, 712 12, 712 20, 712 13, 718102, 718100, 718104, 710 5, 710104, 711147, 711141, 726 21, 726 4, 709225, 717148, 717140, 370395

Abstract:

The disclosure is applied to a generic microprocessor architecture with a set (e. g. , one or more) of controlling elements (e. g. , MPEs) and a set of groups of sub-processing elements (e. g. , SPEs). Under this arrangement, MPEs and SPEs are organized in a way that a smaller number MPEs control the behavior of a group of SPEs using program code embodied as a set of virtualized control threads. The arrangement also enables MPEs delegate functionality to one or more groups of SPEs such that those group(s) of SPEs will act as pseudo MPEs. The pseudo MPEs will utilize pseudo virtualized control threads to control the behavior of other groups of SPEs. In a typical embodiment, the apparatus includes a MCP coupled to a power supply coupled with cores to provide a supply voltage to each core (or core group) and controlling-digital elements and multiple instances of sub-processing elements.

US Patent:

20140259013, Sep 11, 2014

Filed:

May 19, 2014

Appl. No.:

14/281062

Inventors:

- Armonk NY, US
Harm P. Hofstee - Austin TX, US
Daeik Kim - West Lafayette IN, US
Moon J. Kim - Palo Alto CA, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/50
G06F 9/455

US Classification:

718 1

Abstract:

Among other things, the disclosure is applied to a generic microprocessor architecture with a set (e.g., one or more) of controlling/main processing elements (e.g., MPEs) and a set of groups of sub-processing elements (e.g., SPEs). Under this arrangement, MPEs and SPEs are organized in a way that a smaller number MPEs control the behavior of a group of SPEs using program code embodied as a set of virtualized control threads. The apparatus includes a MCP coupled to a power supply coupled with cores to provide a supply voltage to each core (or core group) and controlling-digital elements and multiple instances of sub-processing elements. In accordance with these features, virtualized control threads can traverse the physical boundaries of the MCP to control SPE(s) (e.g., logical partitions having one or more SPEs) in a different physical partition (e.g., different from the physical partition from which the virtualized control threads originated.