Mukesh P Patel

Address:

9217 Robin Lynn Ct, Manassas, VA 20110

VIN:

2T1BR30E87C794547

Make:

TOYOTA

Model:

COROLLA

Year:

2007

US Patent:

6986023, Jan 10, 2006

Filed:

Aug 9, 2002

Appl. No.:

10/215756

Inventors:

Nigel C. Paver - Austin TX, US
William T. Maghielse - Austin TX, US
Wing K. Yu - Chandler AZ, US
Jianwei Liu - Austin TX, US
Anthony Jebson - Austin TX, US
Kailesh B. Bavaria - Austin TX, US
Rupal M. Parikh - Austin TX, US
Deli Deng - Austin TX, US
Mukesh Patel - Austin TX, US
Mark Fullerton - Austin TX, US
Murli Ganeshan - Austin TX, US
Stephen J. Strazdus - Chandler AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 15/16

US Classification:

712 34, 712221, 712223, 712234, 708525

Abstract:

A processor-based system may include a main processor and a coprocessor. The coprocessor handles instructions that include opcodes specifying a data processing operation to be performed by the coprocessor and a coprocessor identification field for identifying a target coprocessor for coprocessor instructions. Two bits indicate one of four data sizes including a byte (8 bits), a half word (16 bits), a word (32 bits), and a double word (64 bits). Two other bits indicate a saturation type.

US Patent:

7013366, Mar 14, 2006

Filed:

Mar 26, 2002

Appl. No.:

10/107947

Inventors:

Rajesh B Patel - Austin TX, US
James David Dundas - Austin TX, US
Mukesh R. Patel - Round Rock TX, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 12/00

US Classification:

711117, 711140, 711154, 712216

Abstract:

A method and apparatus for satisfying load operations by accessing data from a store buffer is described herein. The present invention further relates to satisfying load operations faster than prior art techniques in most cases. Finally, the present invention provides an improved technique for satisfying load operations that does not significantly impact processor performance.

US Patent:

41307666, Dec 19, 1978

Filed:

Oct 13, 1977

Appl. No.:

5/842004

Inventors:

Mukesh P. Patel - Manassas VA

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11C 1928
G11C 1918
H03K 1710
H03K 1716

US Classification:

307221D

Abstract:

An improved bucket brigade circuit is disclosed having an improved transfer efficiency and dynamic range. Conventional bucket brigade circuits consist of a chain of storage capacitors and charge transfer circuits functioning as an analog shift register. Due to the nodal capacitance at the first load of prior art circuits, the charge thereon cannot be maintained at an optimum level because of voltage pull-back and charge redistribution during the fall time of the clock pulse. The invention disclosed herein provides an additional capacitor connecting the first node of the circuit to the inverse of the clock waveform, thereby eliminating the voltage pull-back and charge redistribution problem, resulting in an improved charge transfer efficiency and dynamic range for the circuit.

US Patent:

20200394141, Dec 17, 2020

Filed:

Jun 13, 2019

Appl. No.:

16/440533

Inventors:

- Cambridge, GB
Tushar P. Ringe - Austin TX, US
Mukesh Patel - Round Rock TX, US
Jamshed Jalal - Austin TX, US
Iat Pui Chan - Cedar Park TX, US
Lakshmi Joga Vishnu Vardhan Badukonda - Bee Cave TX, US

Assignee:

Arm Limited - Cambridge

International Classification:

G06F 12/1081
G06F 12/0877
G06F 12/0864

Abstract:

A method and apparatus are provided to enable snoop forwarding to occur together with memory protection. A data processing apparatus in, for instance, the form of a home node forwards a snoop forwarding request on behalf of a requester to a target, the snoop forwarding request being capable of indicating one or more access permissions of the target in relation to the data. A further data processing apparatus in the form of, for instance, a receiver node may receive the snoop forwarding request and based on its own permissions that are provided in the snoop forwarding request, together with the state of the data, either provide a response back to the requester or the home node. In a still further data processing apparatus in the form of, for instance, a Memory Protection Unit (MPU), a regular snoop forwarding request made to a target in relation to data can be forwarded to the target or demoted to a non-forwarding snoop request based on the permissions of the target in relation to the data at the MPU.

US Patent:

20200301854, Sep 24, 2020

Filed:

Mar 22, 2019

Appl. No.:

16/361728

Inventors:

- Cambridge, GB
Tushar P. Ringe - Austin TX, US
Mukesh Patel - Round Rock TX, US
Jamshed Jalal - Austin TX, US
Ashok Kumar Tummala - Cedar Park TX, US
Mark David Werkheiser - Austin TX, US

Assignee:

Arm Limited - Cambridge

International Classification:

G06F 12/14
G06F 12/0817
G06F 9/54

Abstract:

A system, apparatus and method for protecting coherent memory contents in a coherent data processing network by filtering data access requests and snoop response based on the Read/Write (R/W) access permissions. Requests are augmented with access permissions in memory protection units and the access permissions are used to control memory access by home nodes of the network.

US Patent:

20160378701, Dec 29, 2016

Filed:

Jun 26, 2015

Appl. No.:

14/751899

Inventors:

- Santa Clara CA, US
Daniel F. Cutter - Maynard MA, US
Stephen J. Robinson - Austin TX, US
Mukesh K. Patel - Round Rock TX, US

International Classification:

G06F 13/28
G06F 12/08
G06F 13/40

Abstract:

An apparatus having a fabric interconnect that supports multiple topologies and method for using the same are disclosed. In one embodiment, the apparatus comprises mode memory to store information indicative of one of the plurality of modes; and a first fabric operable in a plurality of modes, where the fabric comprises logic coupled to the mode memory to control processing of read and write requests to memory received by the first fabric according to the mode identified by the information indicative.