Murtuza T Lilamwala

US Patent:

20050258994, Nov 24, 2005

Filed:

May 19, 2004

Appl. No.:

10/849659

Inventors:

Murtuza Lilamwala - Aliso Viejo CA, US

International Classification:

H03M001/12

US Classification:

341155000

Abstract:

A direct charge transfer digital to analog converter comprising a single reference voltage linked through a switching structure to a charge accumulation device. An accumulated charge of the charge accumulation system represents the analog output voltage. Use of the single reference voltage in conjunction with the switching structure and charge accumulation system allows for a digital signal to be converted to an analog signal with lower power consumption. Use of a single reference voltage consumes less power and space thereby making it superior to prior art digital to analog conversion systems.

US Patent:

20220200438, Jun 23, 2022

Filed:

Dec 18, 2020

Appl. No.:

17/126814

Inventors:

- San Jose CA, US
Murtuza Lilamwala - San Jose CA, US

Assignee:

Cypress Semiconductor Corporation - San Jose CA

International Classification:

H02M 1/32
H02J 7/06
H02M 7/21
H02M 1/08
H02M 1/36

Abstract:

A system includes a transformer having a primary winding and an auxiliary winding at a primary side of an AC-DC converter, the auxiliary winding reflecting an output voltage of a secondary winding of the transformer. A primary side controller includes an over-voltage protection (OVP) pin and an OVP circuit. A voltage divider includes a first resistor coupled between the auxiliary winding and the OVP pin and a second resistor coupled between the first resistor and a ground. The voltage divider provides, to OVP pin, a reduced voltage that is proportional to the output voltage. In absence of a pulse signal from a secondary side controller, the OVP circuit turns off a gate driver that drives a primary switch in response to the OVP voltage exceeding a reference OVP voltage. The primary switch is coupled between the primary winding of the transformer and the ground.

US Patent:

20220200476, Jun 23, 2022

Filed:

Dec 18, 2020

Appl. No.:

17/127523

Inventors:

- San Jose CA, US
Pavan Kumar Kuchipudi - San Jose CA, US
Myeongseok Lee - Campbell CA, US
Murtuza Lilamwala - San Jose CA, US

Assignee:

Cypress Semiconductor Corporation - San Jose CA

International Classification:

H02M 7/219
G06F 13/42
G06F 1/26
H02J 7/00

Abstract:

A system includes a transformer, a first controller, a discharge circuit to discharge an external capacitor based on an undervoltage threshold, and a second controller. The second controller is coupled to the discharge circuit, and is also coupled to receive a rectified Ac voltage and to receive control signals from the first controller. The second controller includes a gate driver to turn on a primary field effect transistor (FET). The second controller also includes a startup controller coupled to the gate driver. The startup controller is configured to increase a duty cycle of the primary FET based on whether a control signal is received from the first controller. The startup controller is also configured to determine a current duty cycle of the primary FET and to turn off the primary FET based on whether the voltage of the AC-DC converter is above an undervoltage threshold.

US Patent:

20210344193, Nov 4, 2021

Filed:

Apr 29, 2021

Appl. No.:

17/243744

Inventors:

- San Jose CA, US
Henry Yuan - San Ramon CA, US
Mimi Qian - Campbell CA, US
Myeongseok Lee - Campbell CA, US
Sungkwon Lee - Saratoga CA, US
Yan Yi - Mountain View CA, US
Ravindra M. Kapre - San Jose CA, US
Murtuza Lilamwala - San Jose CA, US

Assignee:

Cypress Semiconductor Corporation - San Jose CA

International Classification:

H02H 9/04
H01L 27/02

Abstract:

A system and method for combining positive and negative voltage electrostatic discharge (ESD) protection into a clamp that uses cascoded circuitry, including detecting, by an electrostatic discharge protection system, a voltage pulse on an input pin of an integrated circuit (IC) controller, the IC controller coupled between a power supply node and a ground supply node; determining, by the ESD protection circuit, an ESD event on the input pin based on the voltage detected on the input pin; and/or controlling, by the ESD protection circuit during the ESD event, one or more clamps to transport the voltage pulse from the input pin of the IC controller to the power supply node.