Myung Sun Lee

US Patent:

7751332, Jul 6, 2010

Filed:

Oct 25, 2007

Appl. No.:

11/923777

Inventors:

Yong Liu - San Jose CA, US
Eun Il Seo - Hwaseong-si, KR
Jin Young Yang - Seoul, KR
Myung Jong Lee - New York NY, US
Xuhui Hu - New York NY, US

Assignee:

Samsung Electronics Co., Ltd. - Suwon-si
The Research Foundation of the City University of New York - New York NY

International Classification:

H04L 12/28

US Classification:

370238, 370251, 370254, 709241

Abstract:

A data routing method and system, the data routing method including: locating a destination node using a destination locating packet; establishing a preliminary route including anchor nodes based on a route where the destination locating packet is transmitted to the destination node; determining a link cost between neighbor nodes of each of the anchor nodes, and also between the anchor nodes and the neighbor nodes of each of the anchor nodes; generating minimum cost information with respect to a route consuming a minimum cost from the destination node to a source node using the link cost; and forming a data route from the destination node to the source node using the minimum cost information.

US Patent:

20130290955, Oct 31, 2013

Filed:

Apr 30, 2012

Appl. No.:

13/460836

Inventors:

Yoshio Turner - San Francisco CA, US
Jeongkeun Lee - Mountain View CA, US
Myung Jin Lee - Palo Alto CA, US

International Classification:

G06F 9/455

US Classification:

718 1

Abstract:

Topology input is used to identify a set of data flows as between a set of virtual machines (VMs), as well as one or more network services for one or more of the data flows. A determination is made as to a minimal number of network service virtual machines (NSVMs) for use in providing the one or more network services. An arrangement is determined for server resources and network resources of the data center network on which a virtual network topology is provided for the tenant, including the set of VMs and the number of NSVMs.

US Patent:

20160240457, Aug 18, 2016

Filed:

Feb 18, 2015

Appl. No.:

14/625020

Inventors:

- San Jose CA, US
Myung June Lee - Cupertino CA, US

International Classification:

H01L 23/48
H01L 21/768
H01L 21/56

Abstract:

An integrated circuit package may include a first integrated circuit die attached to a front surface of a second integrated circuit die. An intermediate layer made of a molding compound is formed to surround the second integrated circuit die in a “fan-out” arrangement while leaving a surface of the second integrated circuit die exposed. Accordingly, a group of via holes is then formed in the intermediate layer and filled with a conductive material. Such a configuration forms a dual-sided stacking structure. The stacking structure may also be applicable for package-on-package packages and fan-out wafer-level chip scale packages, in which the stacking structure is formed between two heterogeneous or homogeneous integrated circuit packages.