Nadeem A Kalil

US Patent:

7735030, Jun 8, 2010

Filed:

Jun 29, 2007

Appl. No.:

11/771888

Inventors:

Nadeem Kalil - Southborough MA, US
Philip Giangarra - Medway MA, US
Ritesh Goel - Delhi, IN
Tarun Batra - Delhi, IN

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 17/00
G06F 17/50

US Classification:

716 4, 703 14

Abstract:

A method of simulating a restorable register in a power domain of an RTL (register transfer level) design includes: specifying the power domain in the RTL design, wherein the power domain includes one or more registers and is configured to change power levels separately from other portions of the RTL design; identifying the restorable register in the power domain, wherein the restorable register is updated during power-on operations in the power domain; simulating the restorable register in a power cycle; and saving one or more values from the simulated restorable register. Simulating the restorable register includes: maintaining one or more backup values during a power-off operation for updating the restorable register after the power-off operation; and updating the restorable register during a power-on operation after the power-off operation by using the one or more backup values.