Nagaraj S Palasamudram

US Patent:

54365848, Jul 25, 1995

Filed:

Nov 15, 1993

Appl. No.:

8/152730

Inventors:

Milind A. Bodas - Sunnyvale CA
Nagaraj Palasamudram - San Jose CA
Lavi Lev - San Jose CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03K 17687

US Classification:

327310

Abstract:

A noise suppression circuit for a floating bus in a digital integrated circuit includes pull-up and pull-down feedback loops each connected to the floating bus. The pull-up feedback loop includes a PMOS device connected between a high logic level and the floating bus, with a NOR gate switching the PMOS device. The pull-down feedback loop includes an NMOS device connected between a low logic level and the floating bus, with a NAND gate switches the NMOS device. The NOR and NAND gates are configured such that one of their inputs is connected directly to the floating bus and the other input is connected to the floating bus through an inverter having a finite gate delay. Voltage transitions occurring on the floating bus due to noise injection drive the bus back to its original state before the finite gate delay of the inverter.