Nan Chen

US Patent:

6950359, Sep 27, 2005

Filed:

Mar 28, 2003

Appl. No.:

10/403101

Inventors:

Nan Chen - San Diego CA, US
Cheng Zhong - San Diego CA, US
Mehdi Hamidi Sani - San Diego CA, US

Assignee:

Qualcomm Inc. - San Diego CA

International Classification:

G11C007/00

US Classification:

365203, 365154, 365206

Abstract:

Techniques for replacing and eliminating paths causing channel leakage current. In one embodiment, one or more precharge enable transistors and a precharge enable signal are added to a circuit configuration. The precharge enable transistors are designed to remain on and simply pass a signal in a properly functioning path. When a leakage path is identified, such as during IDDQ testing, the precharge enable signal is set to turn off the precharge enable transistors. When the precharge enable transistors are off, the leakage path is disrupted, and the leakage current stopped. The path may be replaced with a redundant path.

US Patent:

7092307, Aug 15, 2006

Filed:

Aug 14, 2003

Appl. No.:

10/641883

Inventors:

Nan Chen - San Diego CA, US
Cheng Zhong - San Diego CA, US
Mehdi Hamidi Sani - San Diego CA, US

Assignee:

Qualcomm Inc. - San Diego CA

International Classification:

G11C 5/14

US Classification:

365226, 365229

Abstract:

A CMOS integrated circuit (e. g. , an SRAM or a DRAM) is partitioned into a core block, a peripheral block, and a retention block. The core block includes circuits (e. g. , memory cells) that are powered on at all times and is coupled directly to power supply and circuit ground. The peripheral block includes circuits that may be powered on or off and are coupled to the power supply via a head switch and/or to circuit ground via a foot switch. The switches and the core block may be implemented with high threshold voltage (high-Vt) FET devices to reduce leakage current. The peripheral block may be implemented with low-Vt FET devices for high-speed operation. The retention block includes circuits (e. g. , pull-up devices) that maintain signal lines (e. g. , word lines) at a predetermined level so that the internal states of the core block are retained when the peripheral block is powered off.

US Patent:

7859920, Dec 28, 2010

Filed:

Mar 14, 2008

Appl. No.:

12/048676

Inventors:

Chang Ho Jung - San Diego CA, US
Nan Chen - San Diego CA, US
Zhiqin Chen - San Diego CA, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

G11C 7/00
G11C 8/00

US Classification:

36518915, 365194, 365203, 365210, 3652101

Abstract:

A method accurately tracks a bit line maturing time for compiler memory. The method includes enabling a dummy word line in response to an internal clock signal. The dummy word line is enabled prior to enabling a real word line. A dummy bit line is matured in response to enabling of the dummy word line. The dummy bit line matures at a same rate that a real bit line matures. The method also includes disabling the dummy word line in response to determining a threshold voltage differential based on monitoring maturation of the dummy bit line. The real word line is enabled a predefined delay after enabling of the dummy word line. Similarly, the word line is disabled the predefined delay after disabling of the dummy word line. In response to disabling the dummy word line, a sense enable signal is generated.

US Patent:

7872930, Jan 18, 2011

Filed:

May 15, 2008

Appl. No.:

12/121560

Inventors:

Nan Chen - San Diego CA, US
Seong-Ook Jung - Goyang-Si, KR
Zhongze Wang - San Diego CA, US

Assignee:

QUALCOMM, Incorporated - San Diego CA

International Classification:

G11C 29/00

US Classification:

365201, 365154, 36518907

Abstract:

A supply voltage is set for a memory device at a first supply voltage level. Test data is written to the memory device at the first supply voltage level in response to setting the supply voltage. The supply voltage is decreased for the memory device to a second supply voltage level below the first supply voltage level in response to writing the test data. The test data is read from the memory device at the second supply voltage level in response to decreasing the supply voltage. The supply voltage is increased for the memory device to a third supply voltage level above the second supply voltage level in response to reading the test data. The test data is read from the memory device at the third supply voltage level in response to increasing the supply voltage. The test data written to the memory device at the first supply voltage level is compared to the test data read from the memory device at the third supply voltage level in response to reading the test data from the memory device at the third supply voltage level.

US Patent:

7881137, Feb 1, 2011

Filed:

Oct 23, 2008

Appl. No.:

12/256569

Inventors:

Nan Chen - San Diego CA, US
Ritu Chaba - San Diego CA, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

G11C 7/00

US Classification:

365203

Abstract:

A method increases stability of a memory circuit by pre-charging at least one bit line of the memory circuit to a first voltage, pre-charging at least one other bit line of the memory circuit to a second voltage, and equalizing charge across the bit lines so that the bit lines are pre-charged with a third voltage.

US Patent:

7884645, Feb 8, 2011

Filed:

Jan 31, 2008

Appl. No.:

12/023276

Inventors:

Nan Chen - San Diego CA, US
Ritu Chaba - San Diego CA, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

H03K 19/0175

US Classification:

326 81, 326 83, 326 86, 326 87, 327333

Abstract:

In a particular embodiment, a method includes receiving an input voltage at an input to a level shifting circuit that includes voltage pull-up logic. The method includes providing an output signal from the level shifting circuit. The method also includes selectively activating the voltage pull-up logic circuit of the level shifting circuit.

US Patent:

7948824, May 24, 2011

Filed:

Jun 3, 2010

Appl. No.:

12/792982

Inventors:

Changho Jung - San Diego CA, US
Nan Chen - San Diego CA, US
Zhiqin Chen - San Diego CA, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

G11C 8/00

US Classification:

3652331, 36523008, 36523311

Abstract:

A memory device includes a clock buffer circuit. The clock buffer circuit includes a cross-coupled logic circuit. The cross-coupled logic circuit has at least two logic gates in which an output of at least one of the logic gates is coupled to an input of at least one of the logic gates. The cross-coupled logic circuit is coupled to an input for accepting a clock signal. The memory device also includes a clock driver operable to generate a clock signal from the output of the cross-coupled logic circuit. A feedback loop from the clock signal to the cross-coupled logic circuit controls the cross-coupled logic circuit. A buffer circuit including a tri-state inverter is coupled to the clock signal to maintain the clock signal while avoiding contention with the clock generator. The memory device is enabled by a chip select signal.

US Patent:

8000165, Aug 16, 2011

Filed:

Sep 9, 2008

Appl. No.:

12/207011

Inventors:

Changho Jung - San Diego CA, US
Nan Chen - San Diego CA, US
Zhiqin Chen - San Diego CA, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

G11C 8/00

US Classification:

3652331, 36523008, 36523311

Abstract:

A memory device includes a clock buffer circuit. The clock buffer circuit includes a cross-coupled logic circuit. The cross-coupled logic circuit has at least two logic gates in which an output of at least one of the logic gates is coupled to an input of at least one of the logic gates. The cross-coupled logic circuit is coupled to an input for accepting a clock signal. The memory device also includes a clock driver operable to generate a clock signal from the output of the cross-coupled logic circuit. A feedback loop from the clock signal to the cross-coupled logic circuit controls the cross-coupled logic circuit. A buffer circuit including a tri-state inverter is coupled to the clock signal to maintain the clock signal while avoiding contention with the clock generator. The memory device is enabled by a chip select signal.