Nathan D Dias

US Patent:

20040015805, Jan 22, 2004

Filed:

Jul 22, 2002

Appl. No.:

10/200365

Inventors:

David Kidd - San Jose CA, US
Nathan Dias - Sunnyvale CA, US
Matthew Page - San Jose CA, US

International Classification:

G06F017/50

US Classification:

716/012000, 716/013000

Abstract:

In one embodiment, a computer readable medium comprises at least first instructions and second instructions. The first instructions, when executed, compute a first plurality of routes. Each route of the first plurality of routes corresponds to a respective net of a plurality of nets in an integrated circuit layout, and represents a theoretically optimal route of the respective net according to a graph theory based algorithm. The second instructions, when executed, compare each of the first plurality of routes to a corresponding route of a current plurality of routes, each of the current plurality of routes corresponding to the respective net of the plurality of nets and currently existing in the integrated circuit layout. A method is also contemplated.

US Patent:

20050132318, Jun 16, 2005

Filed:

Jan 28, 2005

Appl. No.:

11/046071

Inventors:

David Kidd - San Jose CA, US
Nathan Dias - Sunnyvale CA, US
Matthew Page - San Jose CA, US

International Classification:

G06F017/50

US Classification:

716012000, 716004000

Abstract:

In one embodiment, a computer readable medium comprises at least first instructions and second instructions. The first instructions, when executed, compute a first plurality of routes. Each route of the first plurality of routes corresponds to a respective net of a plurality of nets in an integrated circuit layout, and represents a theoretically optimal route of the respective net according to a graph theory based algorithm. The second instructions, when executed, compare each of the first plurality of routes to a corresponding route of a current plurality of routes, each of the current plurality of routes corresponding to the respective net of the plurality of nets and currently existing in the integrated circuit layout. A method is also contemplated.

US Patent:

20180126356, May 10, 2018

Filed:

Jul 28, 2016

Appl. No.:

15/577775

Inventors:

- San Jose CA, US
Scot BIRMINGHAM - San Francisco CA, US
Nathan DIAS - San Jose CA, US

International Classification:

B01J 20/14
B01J 20/10
B01J 20/28
B01J 20/32
C12H 1/044
B01D 37/02

Abstract:

A chill-proofing composite filter aid may include a filtration component and an adsorption component including precipitated silica at least partially coating the filtration component. The composite filter aid may have a pore volume of at least about 0.15 cm/gram at an average pore size between 3 nanometers and 15 nanometers. A method for removing particles from a fluid may include providing a chill-proofing composite filter aid, pre-coating a filter element with the composite filter aid, and passing a fluid containing particles to be adsorbed through the coated filter element. A method of making a chill-proofing composite filter aid may include providing a filtration component, and at least partially coating the filtration component with an adsorption component including precipitated silica. The composite filter aid may have a pore volume of at least about 0.15 cm/gram at an average pore size between 3 nanometers and 15 nanometers.