Naveen Muralimanohar

US Patent:

8108718, Jan 31, 2012

Filed:

Nov 13, 2009

Appl. No.:

12/618675

Inventors:

Naveen Muralimanohar - Santa Clara CA, US
Norman Paul Jouppi - Palo Alto CA, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 11/00

US Classification:

714 12

Abstract:

One embodiment is a method that performs a local checkpoint at a processing node in a massively parallel processing (MPP) system that executes a workload with a plurality of processing nodes. The local checkpoint is stored in local memory of the processing node. While the workload continues to execute, a global checkpoint is performed from the local checkpoint stored in the local memory.

US Patent:

8392761, Mar 5, 2013

Filed:

Mar 31, 2010

Appl. No.:

12/751005

Inventors:

Matteo Monchiero - Palo Alto CA, US
Naveen Muralimanohar - Santa Clara CA, US
Partha Ranganathan - San Jose CA, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 11/00

US Classification:

714 31, 711114

Abstract:

A system and method is shown that includes a processor operatively connected to a memory, the processor to include a memory controller to control access to the memory. The system and method also includes a service processor, co-located on a common board and operatively connected to the processor and the memory, the service processor to include an additional memory controller to control access to the memory as part of a checkpoint regime.

US Patent:

8516271, Aug 20, 2013

Filed:

Mar 11, 2011

Appl. No.:

13/046381

Inventors:

Paolo Faraboschi - Barcelona, ES
Parthasarathy Ranganathan - San Jose CA, US
Naveen Muralimanohar - Santa Clara CA, US

Assignee:

Hewlett-Packard Development Company, L. P. - Houston TX

International Classification:

H04L 9/14
H04L 9/30

US Classification:

713190, 713164, 713193

Abstract:

Methods, apparatus and articles of manufacture to secure non-volatile memory regions are disclosed. An example method disclosed herein comprises associating a first key pair and a second key pair different than the first key pair with a process, using the first key pair to secure a first region of a non-volatile memory for the process, and using the second key pair to secure a second region of the non-volatile memory for the same process, the second region being different than the first region.

US Patent:

8537634, Sep 17, 2013

Filed:

Nov 13, 2009

Appl. No.:

13/259128

Inventors:

Naveen Muralimanohar - Santa Clara CA, US
Norman Paul Jouppi - Palo Alto CA, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G11C 8/00
G11C 5/02

US Classification:

36523003, 36518902, 365189011, 36518904, 36523002, 36523001

Abstract:

A system and method that includes a memory die, residing on a stacked memory, which is organized into a plurality of mats that include data. The system and method also includes an additional memory die, residing on the stacked memory, that is organized into an additional plurality of mats and connected to the memory die by a Through Silicon Vias (TSVs), the data to be transmitted along the TSVs.

US Patent:

8638600, Jan 28, 2014

Filed:

Apr 22, 2011

Appl. No.:

13/092789

Inventors:

Naveen Muralimanohar - Santa Clara CA, US
Jichuan Chang - Sunnyvale CA, US
Parthasarathy Ranganathan - San Jose CA, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G11C 7/00

US Classification:

365163, 36518914, 36518916

Abstract:

A memory device is provided. The memory device comprises an array of memory cells, each including a volume of material that can stably exhibit at least two different physical states that are each associated with a different data value, word lines that each interconnects a row of memory cells within the array of memory cells to a word-line driver, and bit lines that each interconnects a column of memory cells, through a bit-line driver, to a write driver that is controlled, during a WRITE operation, to write an input data value to an activated memory cell at the intersection of the column of memory cells and an activated row of memory cells by generating a current density within the memory cells that corresponds to retention/endurance characteristics of the memory cell dynamically assigned to the memory cell by a memory controller, operating system, or other control functionality.

US Patent:

8639968, Jan 28, 2014

Filed:

Jan 17, 2011

Appl. No.:

13/007741

Inventors:

Doe Hyun Yoon - Austin TX, US
Naveen Muralimanohar - Santa Clara CA, US
Jichuan Chang - Sunnyvale CA, US
Parthasarathy Ranganathan - San Jose CA, US
Norman Paul Jouppi - Palo Alto CA, US

Assignee:

Hewlett-Packard Development Company, L. P. - Houston TX

International Classification:

G06F 11/00

US Classification:

714 61

Abstract:

Systems, methods, and computer-readable and executable instructions are provided for computing system reliability. A method for computing system reliability can include storing, on one of a plurality of devices, a checkpoint of a current state associated with the one of the plurality of devices. The method may further include storing the checkpoint in an erasure-code group across the plurality of devices.

US Patent:

20070192541, Aug 16, 2007

Filed:

Feb 10, 2006

Appl. No.:

11/351528

Inventors:

Rajeev Balasubramonian - Sandy UT, US
Liqun Cheng - Salt Lake City UT, US
John Carter - Salt Lake City UT, US
Naveen Muralimanohar - Salt Lake City UT, US
Karthik Ramani - Salt Lake City UT, US

International Classification:

G06F 12/00

US Classification:

711118000

Abstract:

A method for utilizing heterogeneous interconnects comprising wires of varying latency, bandwidth and energy characteristics to improve performance and reduce energy consumption by dynamically routing traffic in a processor environment.

US Patent:

20120151159, Jun 14, 2012

Filed:

Jan 27, 2011

Appl. No.:

13/386396

Inventors:

Naveen Muralimanohar - Santa Clara CA, US
Paul Norman Jouppi - Palo Alto CA, US

International Classification:

G06F 12/00

US Classification:

711154, 711E12001

Abstract:

A disclosed example apparatus includes an interface () to receive a request to access a memory () of a memory module () and a data store status monitor () to determine a status of the memory. The example apparatus also includes a message output subsystem () to, when the memory is busy, respond to the request with a negative acknowledgement indicating that the request to access the memory is not grantable.