Neal R Pollack

US Patent:

20220214951, Jul 7, 2022

Filed:

Jan 5, 2021

Appl. No.:

17/141872

Inventors:

- Waltham MA, US
Mustafa Amin - El Segundo CA, US
James Bynes, III - El Segundo CA, US
Patrick Llorens - El Segundo CA, US
Brian Clebowicz - El Segundo CA, US
William Rowe - El Segundo CA, US
Alfredo Lara - El Segundo CA, US
Neal Pollack - El Segundo CA, US

Assignee:

Raytheon Company - Waltham MA

International Classification:

G06F 11/273
G06F 11/22

Abstract:

Fault injection testing for field programmable gate array (FPGA) devices including: interfacing with a FPGA device under test (DUT); imaging a configuration RAM (CRAM) of the FPGA DUT with a first configuration image to define a first operational function of the FPGA DUT where the CRAM includes a plurality of CRAM bits, injecting a plurality of single event upsets into a portion of the plurality of the CRAM bits while the FPGA DUT is operating; concurrently monitoring operations of the FPGA DUT and a reference FPGA device; comparing outputs of the FPGA DUT with outputs of the reference FPGA device during concurrent operations, and if there is a mismatch between the outputs of the FPGA DUT and the reference FPGA, determining that error events have occurred within the FPGA DUT; and storing the error events and CRAM location data associated with corresponding single event upsets in an error log.