Neil R Richardson

US Patent:

6445199, Sep 3, 2002

Filed:

Aug 25, 2000

Appl. No.:

09/648379

Inventors:

Akella V. S. Satya - Milpitas CA
Brian C. Leslie - Cupertino CA
Gustavo A. Pinto - Belmont CA
Robert Thomas Long - Santa Cruz CA
Neil Richardson - Palo Alto CA

Assignee:

KLA-Tencor Corporation - San Jose CA

International Classification:

G01R 31308

US Classification:

324753, 324751, 324752, 324759, 324537

Abstract:

Disclosed is a method of inspecting a sample. The sample is illuminated with an incident beam, thereby causing voltage contrast within structures present on the sample. Voltage contrast is detected within the structures. Information from the detected voltage contrast is stored, and position data concerning the location of features corresponding to at least a portion of the stored voltage contrast information is also stored. In a specific embodiment, the features represent electrical defects present on the sample. In another embodiment, the stored position data is in the form of a two dimensional map. In another aspect, the sample is re-inspected and the stored position data is used in analyzing data resulting from the re-inspection.

US Patent:

6509197, Jan 21, 2003

Filed:

Aug 25, 2000

Appl. No.:

09/648212

Inventors:

Akella V. S. Satya - Milpitas CA
Robert Thomas Long - Santa Cruz CA
Lynda C. Mantalas - Campbell CA
Gustavo A. Pinto - Belmont CA
Neil Richardson - Palo Alto CA

Assignee:

KLA-Tencor Corporation - San Jose CA

International Classification:

H01L 2100

US Classification:

438 12

Abstract:

Disclosed is a semiconductor die having a lower test structure formed in a lower metal layer of the semiconductor die. The lower conductive test structure has a first end and a second end. The first end is coupled to a predetermined voltage level. The semiconductor die also includes an insulating layer formed over the lower metal layer. The die further includes an upper test structure formed in an upper metal layer of the semiconductor die. The upper conductive test structure is coupled with the second end of the lower conductive test structure. The upper metal layer is formed over the insulating layer. In a specific implementation, the first end of the lower test structure is coupled to ground. In another embodiment, the semiconductor die also includes a substrate and a first via coupled between the first end of the lower test structure and the substrate. In yet another aspect, the lower test structure is an extended metal line, and the upper test structure is a voltage contrast element.

US Patent:

6524873, Feb 25, 2003

Filed:

Aug 25, 2000

Appl. No.:

09/648094

Inventors:

Akella V. S. Satya - Milpitas CA
David L. Adler - San Jose CA
Neil Richardson - Palo Alto CA
David J. Walker - Sunol CA

Assignee:

KLA-Tencor - San Jose CA

International Classification:

G01R 3126

US Classification:

438 18

Abstract:

Disclosed is, a method for detecting electrical defects on test structures of a semiconductor die. The semiconductor die includes a plurality of electrically-isolated test structures and a plurality of non-electrically-isolated test structures. Voltages are established for the plurality of electrically-isolated test structures. These voltages are different than the voltages of the plurality of non-electrically-isolated test structures. A region of the semiconductor die is continuously inspected in a first direction thereby obtaining voltage contrast data indicative of whether there are defective test structures. The voltage contrast data is analyzed to determine whether there are one or more defective test structures.

US Patent:

6528818, Mar 4, 2003

Filed:

Aug 25, 2000

Appl. No.:

09/648380

Inventors:

Akella V. S. Satya - Milpitas CA
Gustavo A. Pinto - Belmont CA
David L. Adler - San Jose CA
Robert Thomas Long - Santa Cruz CA
Neil Richardson - Palo Alto CA
Kurt H. Weiner - San Jose CA
David J. Walker - Sunol CA
Lynda C. Mantalas - Campbell CA

Assignee:

KLA-Tencor - San Jose CA

International Classification:

H01L 2358

US Classification:

257 48, 257758

Abstract:

Disclosed is a semiconductor die having a scanning area. The semiconductor die includes a first plurality of test structures wherein each of the test structures in the first plurality of test structures is located entirely within the scanning area. The semiconductor die further includes a second plurality of test structures wherein each of the test structures in the first plurality of test structures is located only partially within the scanning area. The test structures are arranged so that a scan of the scanning area results in detection of defects outside of the scanning area.

US Patent:

6576923, Jun 10, 2003

Filed:

Jun 21, 2002

Appl. No.:

10/178329

Inventors:

Akella V. S. Satya - Milpitas CA
Robert Thomas Long - Santa Cruz CA
Lynda C. Mantalas - Campbell CA
Gustavo A. Pinto - Belmont CA
Neil Richardson - Palo Alto CA

Assignee:

KLA-Tencor Corporation - San Jose CA

International Classification:

H01L 2358

US Classification:

257 48, 438 11, 438 14, 438 18

Abstract:

Disclosed is a semiconductor die having a lower test structure formed in a lower metal layer of the semiconductor die. The lower conductive test structure has a first end and a second end. The first end is coupled to a predetermined voltage level. The semiconductor die also includes an insulating layer formed over the lower metal layer. The die further includes an upper test structure formed in an upper metal layer of the semiconductor die. The upper conductive test structure is coupled with the second end of the lower conductive test structure. The upper metal layer is formed over the insulating layer. In a specific implementation, the first end of the lower test structure is coupled to ground. In another embodiment, the semiconductor die also includes a substrate and a first via coupled between the first end of the lower test structure and the substrate. In yet another aspect, the lower test structure is an extended metal line, and the upper test structure is a voltage contrast element.

US Patent:

6627884, Sep 30, 2003

Filed:

Jul 23, 2001

Appl. No.:

09/912732

Inventors:

Mark A. McCord - Mountain View CA
David Walker - Sunol CA
Jun Pei - Campbell CA
Neil Richardson - Palo Alto CA

Assignee:

KLA-Tencor Technologies Corporation - Milpitas CA

International Classification:

G21K 700

US Classification:

250306, 250305, 250302, 250310, 250251, 378 84, 378 85

Abstract:

Disclosed are methods and apparatus for simultaneously flooding a sample (e. g. , a semiconductor wafer) to control charge and inspecting the sample. The apparatus includes a charged particle beam generator arranged to generate a charged particle beam substantially towards a first portion of the sample and a flood gun for generating a second beam towards a second portion of the sample. The second beam is generated substantially simultaneously with the inspection beam. The apparatus further includes a detector arranged to detect charged particles originating from the sample portion. In a further implementation, the apparatus further includes an image generator for generating an image of the first portion of the sample from the detected particles. In one embodiment, the sample is a semiconductor wafer. In a method aspect, a first area of a sample is flooded with a flood beam to control charge on a surface of the sample.

US Patent:

6633174, Oct 14, 2003

Filed:

Aug 25, 2000

Appl. No.:

09/648093

Inventors:

Akella V. S. Satya - Milpitas CA
David L. Adler - San Jose CA
Neil Richardson - Palo Alto CA
Gustavo A. Pinto - Belmont CA
David J. Walker - Sunol CA

Assignee:

KLA-Tencor - San Jose CA

International Classification:

G01R 31305

US Classification:

324751, 324753, 3241581

Abstract:

Disclosed is a method of inspecting a sample. The method includes moving to a first field associated with a first group of test structures. The first group of test structures are partially within the first field. The method further includes scanning the first field to determine whether there are any defects present within the first group of test structures. When it is determined that there are defects within the first group of test structures, the method further includes repeatedly stepping to areas and scanning such areas so as to determine a specific defect location within the first group of test structures. A suitable test structure for performing this method is also disclosed.

US Patent:

6636064, Oct 21, 2003

Filed:

Aug 25, 2000

Appl. No.:

09/648092

Inventors:

Akella V. S. Satya - Milpitas CA
David L. Adler - San Jose CA
Neil Richardson - Palo Alto CA
Kurt H. Weiner - San Jose CA
David J. Walker - Sunol CA

Assignee:

KLA-Tencor - San Jose CA

International Classification:

G01R 3128

US Classification:

324763, 324751, 324765

Abstract:

Disclosed is a semiconductor die having an upper layer and a lower layer. The die includes a lower test structure formed in the lower metal layer of the semiconductor die. The lower conductive test structure has a first end and a second end, wherein the first end is coupled to a predetermined voltage level. The die also has an insulating layer formed over the lower metal layer and an upper test structure formed in the upper metal layer of the semiconductor die. The upper conductive test structure is coupled with the second end of the lower conductive test structure, and the upper metal layer being formed over the insulating layer. The die further includes at least one probe pad coupled with the upper test structure. Preferably, the first end of the lower test structure is coupled to a nominal ground potential. In another implementation, the upper test structure is a voltage contrast element.