Ning Lu

US Patent:

20220181434, Jun 9, 2022

Filed:

Dec 9, 2020

Appl. No.:

17/116120

Inventors:

- Boise ID, US
Hung-Wei Liu - Meridian ID, US
Ning Lu - Boise ID, US
Anish A. Khandekar - Boise ID, US
Jeffery B. Hull - Boise ID, US
Silvia Borsari - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 29/04
H01L 29/786

Abstract:

A vertical transistor comprises a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region. The top source/drain region and the channel region have a top interface and the bottom source/drain region and the channel region have a bottom interface. The channel region is crystalline and has an average crystal grain size of its crystal grains that is less than 20 nanometers. The channel region at the top interface or at the bottom interface has greater horizontal texture than volume of the crystal grains in the channel region that is vertically between the crystal grains that are at the top and bottom interfaces. Other embodiments and aspects are disclosed.