Cyient
Physical Design Engineer
Infotech Enterprises It Services Pvt Ltd ( Infotech It ) Oct 2012 - Jun 2013
Senior Pde
Cyient Oct 2010 - Jun 2013
Team Lead
Wipro Technologies Jun 2006 - Aug 2009
Software Engineer
Network Programs Aug 2005 - Apr 2006
Mts
Education:
Jawaharlal Nehru Technological University 2001 - 2004
Masters
Karnataka Law College, Dharwad 1995 - 1999
Bachelors
Skills:
Vlsi Physical Design Asic Static Timing Analysis Debugging Microprocessors Verilog Soc Tcl C Embedded Systems Timing Closure Functional Verification Rtl Coding Systemverilog Eda Dft Modelsim Logic Synthesis Ic Rtl Design Floorplanning Low Power Design Very Large Scale Integration Physical Verification Microcontrollers Vhdl Application Specific Integrated Circuits System on A Chip Perl Semiconductors Fpga Integrated Circuit Design C++