Norman S Dancer

US Patent:

6467015, Oct 15, 2002

Filed:

Apr 11, 2002

Appl. No.:

10/122113

Inventors:

Shari J. Nolan - San Jose CA
Jeffery S. Nespor - Pleasanton CA
Norman S. Dancer - San Jose CA
Everett E. Groff - San Jose CA
James W. Frandeen - Soquel CA

Assignee:

Dell Products, L.P. - Round Rock TX

International Classification:

G06F 1300

US Classification:

711 5, 711154, 711157, 711167, 710 52, 710129, 710130, 36523003

Abstract:

A memory system with non-volatile integrated circuit memory devices including an interface for a high speed bus is described, supporting continuous writes at the bus speed, without the possibility of buffer overrun during most conditions. The system comprises an memory bus, an system buffer, an array of non-volatile storage units, such as flash memory devices, and an interconnect system supporting data transfer among the components. The array includes sets and subsets of non-volatile storage units, referred to herein for convenience as platters having multiple banks, banks having multiple columns, and columns having multiple storage units. The storage units comprises integrated circuit memory having page buffers, with input ports. In one example, the array includes two platters, eight banks per platter, four columns per bank, and eight storage units per column, for a total of 256 storage units. The system buffer includes at least the same number of stores as columns in each bank.

US Patent:

6401161, Jun 4, 2002

Filed:

Apr 15, 1999

Appl. No.:

09/292536

Inventors:

Shari J. Nolan - San Jose CA
Jeffery S. Nespor - Pleasanton CA
Norman S. Dancer - San Jose CA
Everett E. Groff - San Jose CA
James W. Frandeen - Soquel CA
Gregory Scott Triplett - Pleasanton CA

Assignee:

Dell Products, LP - Round Rock TX

International Classification:

G06F 1300

US Classification:

711 5, 711154, 711157, 711167, 710 52, 710129, 710130, 36523003

Abstract:

An apparatus is described, comprising a plurality of banks, each bank having a number of columns of non-volatile storage units, each non-volatile storage unit having an input buffer for storing a page of data, the page having an input coupled to the input buffer accepting an input portion of data of a page at a memory speed, the non-volatile storage units storing the data from the input buffer within a memory write time; a plurality of interface buffers; an input bus having an input bus speed which is faster than the memory speed, the input bus being coupled to the plurality of interface buffers; a bus system, connecting each of the plurality of interface buffers to the non-volatile storage units of a column in each of the plurality of banks, supplying data from the plurality of interface buffers to the inputs of the non-volatile storage units at the memory speed.