Olga A Kobozeva

US Patent:

20040250232, Dec 9, 2004

Filed:

Jun 3, 2003

Appl. No.:

10/453182

Inventors:

Olga Kobozeva - Los Altos CA, US
Mario Garza - San Jose CA, US
Ramnath Venkatraman - San Jose CA, US

International Classification:

G06F017/50

US Classification:

716/019000, 716/004000

Abstract:

A method of silicon design reproducibility enhancement using priority assignments prior to performing a conventional optical proximity correction process on a device. The present invention seeks to improve the manufacturability of VLSI devices. The present invention inserts a priority assignment step prior to the conventional OPC correction process in order to assert better control over transistor parameters. The priority assignment step sorts the layout by degree of importance to the cell/device performance. Areas designated as critical are given higher priority values while areas designated as non-critical are given lower priority values. The present invention imposes more precise accuracy requirements to high priority value areas and less precise accuracy requirements to low priority value areas. As a result, the present invention imposes the tightest accuracy requirements to critical areas of device performance, rather than attempting to achieve overall accuracy during the OPC correction process.