Ook Kim

US Patent:

6693985, Feb 17, 2004

Filed:

Oct 26, 2001

Appl. No.:

10/043886

Inventors:

Hung Sung Li - Sunnyvale CA
Ook Kim - Palo Alto CA

Assignee:

Silicon Image - Sunnyvale CA

International Classification:

H04L 700

US Classification:

375355, 375371, 327144

Abstract:

Embodiments of a clock and data recovery method and apparatus include receiving a multi-channel serial digitally encoded signal and converting the received signal to digital data, or set of binary characters. One embodiment includes determining whether a phase of a sampling circuit is appropriate to sample meaningful data from a received signal; if the phase of the sampling circuit is not appropriate, the phase is shifted so that sampling occurs earlier or later for the received signal. The determination is based, in one embodiment, on the order and value of the samples taken, which indicate whether the samples are taken too close to a transition of the received signal.

US Patent:

6717478, Apr 6, 2004

Filed:

Nov 20, 2001

Appl. No.:

09/989587

Inventors:

Ook Kim - Palo Alto CA
Hung Sung Li - Sunnyvale CA
Inyeol Lee - Cupertino CA
Gyudong Kim - San Jose CA
Yongman Lee - Pleasanton CA

Assignee:

Silicon Image - Sunnyvale CA

International Classification:

H03B 2700

US Classification:

331 57, 331 46

Abstract:

A voltage controlled oscillator (âVCOâ) circuit capable of generating signals with reduced jitter and/or low-phase noise is provided. One embodiment provides a plurality of cascaded VCO cells, where each VCO cell can include a source coupled differential pair, a bias transistor connected to the differential pair for biasing the differential pair, a resistive load pair connected to the differential pair, and a voltage controlled capacitor pair or varactor pair connected to the differential pair. The varactors provide control over the frequency of the oscillations produced by the VCO circuit in combination with a control voltage. A phase frequency detector combined with a charge pump and loop filter provide the control voltage.

US Patent:

6809567, Oct 26, 2004

Filed:

Nov 20, 2001

Appl. No.:

09/989645

Inventors:

Ook Kim - Palo Alto CA
Hung Sung Li - Sunnyvale CA
Inyeol Lee - Cupertino CA
Gyudong Kim - San Jose CA
Yongman Lee - Pleasanton CA

Assignee:

Silicon Image - Sunnyvale CA

International Classification:

H03L 700

US Classification:

327160, 327115, 327117, 327295

Abstract:

A system and method for multiple-phase clock generation is disclosed. In one embodiment, a multiple-stage voltage controlled oscillator (âVCOâ) transmits a plurality of clock phases to a clock divider circuit which produces the desired number of clock phase outputs. The clock divider circuit in this embodiment includes a state machine, e. g. , a modified Johnson counter, that provides a plurality of divided down clock phases, each of which is connected to a separate modified shift register. Each modified shift register contains D-type flip-flops and each D-type flip-flop provides a separate clock phase output. In one embodiment the number of clock phase outputs of the multiple-phase clock is a function of the number of VCO clock phases times the number of desired states in the modified Johnson counter.

US Patent:

6845461, Jan 18, 2005

Filed:

Nov 20, 2001

Appl. No.:

09/989590

Inventors:

Ook Kim - Palo Alto CA, US

Assignee:

Silicon Image, Inc. - Sunnyvale CA

International Classification:

G06F 1314

US Classification:

713500, 710316, 710305

Abstract:

A system and method for embedding at least one clock signal into bus lines that also carry data signals at other times to enable a high-speed bus is disclosed. Each bus line is used for carrying both clock and data information at different times. Data signals, which may be either encoded or not, are carried through a subset of the bus lines through a mapping scheme that maps the data information to the bus lines at each data transfer while the clock signals are carried in the remaining bus lines. Various mapping schemes are possible.

US Patent:

7062004, Jun 13, 2006

Filed:

Jul 13, 2001

Appl. No.:

09/905511

Inventors:

Gyudong Kim - San Jose CA, US
Min-Kyu Kim - Cupertino CA, US
Ook Kim - Palo Alto CA, US
Eric A. Lee - San Jose CA, US
Bruce Kim - Los Altos CA, US

Assignee:

Silicon Image, Inc. - Sunnyvale CA

International Classification:

H04L 7/00

US Classification:

375371, 375376

Abstract:

A scheme for reducing jitter in high-speed digital communication by adaptively controlling the loop bandwidth of a receiver PLL to reduce the relative jitter between the recovered data and clock. The scheme uses phase pointer activity to represent the relative jitter. The phase pointer activity is measured and used to control the receiver PLL loop bandwidth. The receiver PLL loop bandwidth is repeatedly incremented or decremented by a step size based on the comparison between a newly measured activity value and the old activity value, until the phase pointer activity reaches a minimum. Because the PLL performance requirement of the transmitter can be relaxed, compatibility with legacy transmitters and multi-vendor transmitters is enhanced. Because tight control of fabrication process parameters of PLLs may be relaxed, the fabrication yield may also be improved.

US Patent:

7158593, Jan 2, 2007

Filed:

Mar 15, 2002

Appl. No.:

10/099533

Inventors:

Gyudong Kim - Sunnyvale CA, US
Ook Kim - Palo Alto CA, US
Min-Kyu Kim - Cupertino CA, US
Bruce Kim - Los Altos CA, US
Seung Ho Hwang - Palo Alto CA, US

Assignee:

Silicon Image, Inc. - Sunnyvale CA

International Classification:

H04L 7/00

US Classification:

375354

Abstract:

A method of transmitting data in a system including at least one data channel and a separate clock channel is disclosed. The method involves combining a clock signal to be transmitted on the clock channel with a data signal to generate a combined clock and data signal. In one embodiment, the data signal has been generated from data words using an encoding scheme that shifts an energy spectrum of the data signal away from an energy spectrum of the clock signal. In another embodiment, the clock signal has a plurality of pulses each having a front edge and a back edge, and the data signal is modulated onto the clock signal by moving at least one edge (i. e. front or back or both) of the plurality of pulses, thereby to create a combined clock and data signal.

US Patent:

7500032, Mar 3, 2009

Filed:

Aug 31, 2007

Appl. No.:

11/848758

Inventors:

Ook Kim - Palo Alto CA, US
Eric Lee - San Jose CA, US
Gyudong Kim - Sunnyvale CA, US
Baegin Sung - Sunnyvale CA, US
Nam Hoon Kim - Cupertino CA, US
Gijung Ahn - San Jose CA, US
Seung Ho Hwang - Palo Alto CA, US

Assignee:

Silicon Image, Inc - Sunnyvale CA

International Classification:

G06F 13/38

US Classification:

710 72

Abstract:

A cable including circuitry for asserting information to a user or external device and a system including such a cable. The cable can include conductors, a memory storing cable data, and circuitry configured to respond to a request received on at least one of the conductors by accessing at least some of the cable data and asserting the accessed data serially to at least one of the conductors (e. g. , for transmission to an external device). Other aspects of the invention are methods for accessing cable data stored in a cable and optionally using the data (e. g. , to implement equalization). The cable data can be indicative of all or some of cable type, grade, speed, length, and impedance, a date code, a frequency-dependent attenuation table, far-end crosstalk and EMI-related coefficients, common mode radiation, intra pair skew, and other information. The cable can include a radiation-emitting element and circuitry for generating driving signals for causing the radiation-emitting element to produce an appropriate color, brightness, and/or blinking pattern.

US Patent:

7502411, Mar 10, 2009

Filed:

Mar 5, 2004

Appl. No.:

10/794015

Inventors:

Ook Kim - Palo Alto CA, US
Gyudong Kim - Sunnyvale CA, US

Assignee:

Silicon Image, Inc. - Sunnyvale CA

International Classification:

H03H 7/30
H03H 7/40

US Classification:

375229, 375230, 375231, 375232, 375233, 375234, 375235, 375236, 375316

Abstract:

In preferred embodiments, an adaptive equalization circuit including at least two equalization filters (each for equalizing a signal transmitted over a multi-channel serial link) and control circuitry for generating an equalization control signal for use by all the filters. The control circuitry generates the control signal in response to an equalized signal produced by one of the filters, and asserts the control signal to all the filters. Preferably, one filter generates an equalized fixed pattern signal in response to a fixed pattern signal (e. g. , a clock signal), each other filter equalizes a data signal, and the control circuitry generates the control signal in response to the equalized fixed pattern signal. In other embodiments, the invention is an adaptive equalization circuit including an equalization filter and circuitry for generating a control signal for the filter in response to a signal indicative of a predetermined fixed pattern, a receiver including an adaptive equalization circuit, a system including such a receiver, and a method for adaptive equalization of signals received over a multi-channel serial link.