Owen Yin Loh

US Patent:

20110317325, Dec 29, 2011

Filed:

Jun 16, 2011

Appl. No.:

13/134787

Inventors:

Horacio D. Espinosa - Winnetka IL, US
Owen Y. Loh - Portland OR, US
Xiaoding Wei - Evanston IL, US

International Classification:

H01H 47/22
H02N 1/08
H05K 3/00
B82Y 40/00
B82Y 15/00

US Classification:

361211, 310300, 29832, 977902

Abstract:

The present invention provides for replacement of conventionally-used metal electrodes in NEMS devices with electrodes that include non-metallic materials comprised of diamond-like carbon or a dielectric coated metallic film having greater electrical contact resistance and lower adhesion with a contacting nanostructure. This reduces Joule heating and stiction, improving device reliability.

US Patent:

20210167182, Jun 3, 2021

Filed:

Dec 2, 2019

Appl. No.:

16/700757

Inventors:

- Santa Clara CA, US
Ashish Verma PENUMATCHA - Beaverton OR, US
Devin MERRILL - McMinnville OR, US
I-Cheng TUNG - Hillsboro OR, US
Jack T. KAVALIEROS - Portland OR, US
Ian A. YOUNG - Portland OR, US
Matthew V. METZ - Portland OR, US
Uygar E. AVCI - Portland OR, US
Chia-Ching LIN - Portland OR, US
Owen LOH - Portland OR, US
Shriram SHIVARAMAN - Hillsboro OR, US
Eric Charles MATTSON - Portland OR, US

International Classification:

H01L 29/51
H01L 29/78
H01L 29/66
H01L 27/088
H01L 29/423
H01L 21/8234

Abstract:

A integrated circuit structure comprises a fin extending from a substrate. The fin comprises source and drain regions and a channel region between the source and drain regions. A multilayer high-k gate dielectric stack comprises at least a first high-k material and a second high-k material, the first high-k material extending conformally over the fin over the channel region, and the second high-k material conformal to the first high-k material, wherein either the first high-k material or the second high-k material has a modified material property different from the other high-k material, wherein the modified material property comprises at least one of ferroelectricity, crystalline phase, texturing, ordering orientation of the crystalline phase or texturing to a specific crystalline direction or plane, strain, surface roughness, and lattice constant and combinations thereof. A gate electrode ix over and on a topmost high-k material in the multilayer high-k gate dielectric stack. A selector element is above the metal layer.

US Patent:

20200312949, Oct 1, 2020

Filed:

Mar 28, 2019

Appl. No.:

16/368450

Inventors:

- Santa Clara CA, US
Chia-Ching LIN - Portland OR, US
Ashish Verma PENUMATCHA - Hillsboro OR, US
Owen LOH - Portland OR, US
Mengcheng LU - Portland OR, US
Seung Hoon SUNG - Portland OR, US
Ian A. YOUNG - Portland OR, US
Uygar AVCI - Portland OR, US
Jack T. KAVALIEROS - Portland OR, US

International Classification:

H01L 49/02
H01G 4/30
H01G 4/012
H01L 27/11585
H01L 23/522

Abstract:

A capacitor is disclosed. The capacitor includes a first metal layer, a second metal layer on the first metal layer, a ferroelectric layer on the second metal layer, and a third metal layer on the ferroelectric layer. The second metal layer includes a first non-reactive barrier metal and the third metal layer includes a second non-reactive barrier metal. A fourth metal layer is on the third metal layer.

US Patent:

20200312950, Oct 1, 2020

Filed:

Mar 29, 2019

Appl. No.:

16/369737

Inventors:

- Santa Clara CA, US
Chia-Ching LIN - Portland OR, US
Ashish Verma PENUMATCHA - Hillsboro OR, US
Owen LOH - Portland OR, US
Mengcheng LU - Portland OR, US
Seung Hoon SUNG - Portland OR, US
Ian A. YOUNG - Portland OR, US
Uygar AVCI - Portland OR, US
Jack T. KAVALIEROS - Portland OR, US

International Classification:

H01L 49/02
H01L 27/11585
H01L 23/522
H01G 4/30
H01G 4/012

Abstract:

A capacitor is disclosed that includes a first metal layer and a seed layer on the first metal layer. The seed layer includes a polar phase crystalline structure. The capacitor also includes a ferroelectric layer on the seed layer and a second metal layer on the ferroelectric layer.

US Patent:

20200312976, Oct 1, 2020

Filed:

Mar 25, 2019

Appl. No.:

16/363632

Inventors:

- Santa Clara CA, US
Jack Kavalieros - Portland OR, US
Ian Young - Portland OR, US
Matthew Metz - Portland OR, US
Uygar Avci - Portland OR, US
Devin Merrill - McMinnville OR, US
Ashish Verma Penumatcha - Hillsboro OR, US
Chia-Ching Lin - Portland OR, US
Owen Loh - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 29/49
H01L 29/51
H01L 29/78
H01L 21/28
H01L 29/66

Abstract:

Techniques and mechanisms to provide electrical insulation between a gate and a channel region of a non-planar circuit device. In an embodiment, the gate structure, and insulation spacers at opposite respective sides of the gate structure, each extend over a semiconductor fin structure. In a region between the insulation spacers, a first dielectric layer extends conformally over the fin, and a second dielectric layer adjoins and extends conformally over the first dielectric layer. A third dielectric layer, adjoining the second dielectric layer and the insulation spacers, extends under the gate structure. Of the first, second and third dielectric layers, the third dielectric layer is conformal to respective sidewalls of the insulation spacers. In another embodiment, the second dielectric layer is of dielectric constant which is greater than that of the first dielectric layer, and equal to or less than that of the third dielectric layer.

US Patent:

20200312978, Oct 1, 2020

Filed:

Mar 25, 2019

Appl. No.:

16/363952

Inventors:

- Santa Clara CA, US
Ian YOUNG - Portland OR, US
Matthew METZ - Portland OR, US
Uygar AVCI - Portand OR, US
Chia-Ching LIN - Portland OR, US
Owen LOH - Portland OR, US
Seung Hoon SUNG - Portland OR, US
Aditya KASUKURTI - Hillsboro OR, US
Tanay GOSAVI - Hillsboro OR, US
Ashish Verma PENUMATCHA - Hillsboro OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 29/51
H01L 29/66
H01L 29/78
G09G 3/36
G02F 1/141
H01L 21/28

Abstract:

Techniques and mechanisms for providing electrical insulation or other protection of an integrated circuit (IC) device with a spacer structure which comprises an (anti)ferromagnetic material. In an embodiment, a transistor comprises doped source or drain regions and a channel region which are each disposed in a fin structure, wherein a gate electrode and an underlying dielectric layer of the transistor each extend over the channel region. Insulation spacers are disposed on opposite sides of the gate electrode, where at least a portion of one such insulation spacer comprises an (anti)ferroelectric material. Another portion of the insulation spacer comprises a non-(anti)ferroelectric material. In another embodiment, the two portions of the spacer are offset vertically from one another, wherein the (anti)ferroelectric portion forms a bottom of the spacer.

US Patent:

20200286685, Sep 10, 2020

Filed:

Mar 6, 2019

Appl. No.:

16/294811

Inventors:

- Santa Clara CA, US
Ashish Verma Penumatcha - Hillsboro OR, US
Seung Hoon Sung - Portland OR, US
Owen Y. Loh - Portland OR, US
Jack Kavalieros - Portland OR, US
Uygar E. Avci - Portland OR, US
Ian A. Young - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01G 7/06
H01L 49/02
H01L 27/108

Abstract:

Described is a ferroelectric based capacitor that reduces non-polar monoclinic phase and increases polar orthorhombic phase by epitaxial strain engineering in the oxide thin film and/or electrodes. As such, both memory window and reliability are improved. The capacitor comprises: a first structure comprising metal, wherein the first structure has a first lattice constant; a second structure comprising metal, wherein the second structure has a second lattice constant; and a third structure comprising ferroelectric material (e.g., oxide of Hf or Zr), wherein the third structure is between and adjacent to the first and second structures, wherein the third structure has a third lattice constant, and wherein the first and second lattice constants are smaller than the third lattice constant.

US Patent:

20200286686, Sep 10, 2020

Filed:

Mar 7, 2019

Appl. No.:

16/296082

Inventors:

- Santa Clara CA, US
Ashish Verma Penumatcha - Hillsboro OR, US
Seung Hoon Sung - Portland OR, US
Owen Y. Loh - Portland OR, US
Jack Kavalieros - Portland OR, US
Uygar E. Avci - Portland OR, US
Ian A. Young - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01G 7/06
H01L 49/02
H01L 27/108

Abstract:

Described is a ferroelectric-based capacitor that improves reliability of a ferroelectric memory by using low-leakage insulating thin film. In one example, the low-leakage insulating thin film is positioned between a bottom electrode and a ferroelectric oxide. In another example, the low-leakage insulating thin film is positioned between a top electrode and ferroelectric oxide. In yet another example, the low-leakage insulating thin film is positioned in the middle of ferroelectric oxide to reduce the leakage current and improve reliability of the ferroelectric oxide.