Parminder Singh Gill

US Patent:

6763437, Jul 13, 2004

Filed:

Sep 7, 2000

Appl. No.:

09/656529

Inventors:

Trung Nguyen - San Jose CA
Hang Nguyen - Fremont CA
John W. Brooks - San Jose CA
Parminder K. Gill - Fremont CA

Assignee:

Maxtor Corporation - Longmont CO

International Classification:

G06F 1336

US Classification:

711147, 151158, 151112

Abstract:

A method and system of providing access to a shared memory interconnected to a first controller and a second controller via a bus, the bus having control signals associated therewith for data transfer control and communication between the first and the second controllers. The second controller transmits an access request to the first controller for control of the bus to access the memory. The first controller selectively grants the access request and transmits an acknowledge to the second controller; and upon receiving the acknowledge, the second controller accesses the memory for data transfer. The first controller has a first priority for accessing the memory, and the second controller has a second priority for accessing the memory, the second priority being lower than the first priority such that upon request the first controller selectively grants control of the bus to the second controller for memory access, otherwise the first controller maintains control of the bus for memory access. In one embodiment, the second controller transmits an access request to the first controller for control of the bus to access the memory; and in response, the first controller selectively grants the access request and transmits an acknowledge to the second controller. Each of the controllers relinquishes control of the bus by placing the bus in tristate, wherein the relinquishing controller stops driving the bus.

US Patent:

61784869, Jan 23, 2001

Filed:

Feb 19, 1998

Appl. No.:

9/026472

Inventors:

Parminder Gill - Fremont CA
Clifford M. Gold - Fremont CA
James A. Henson - Morgan Hill CA

Assignee:

Quantum Corporation - Milpitas CA

International Classification:

G06F 1200

US Classification:

711151

Abstract:

A method and apparatus for arbitrating requests for access to a single buffer memory embedded within a disk drive in which a disk data channel is assigned a highest priority for buffer access within a queue. An arbitration cycle progressively services access requests pending within the queue, beginning with providing buffer access to the disk data channel and following with accesses to other channels during an arbitration cycle completion interval in accordance with a round-robin circular priority arrangement providing orderly access to all channels contending for memory access. At the end of completion interval, buffer access returns to the disk data channel, and thereafter, the arbitration cycle is repeated.