An ultra-large scale CMOS integrated circuit semiconductor device with LDD structures is manufactured by forming a gate oxide layer over the semiconductor substrate; forming a polysilicon layer over the gate oxide layer; forming a first mask layer over the polysilicon layer; patterning and etching the first mask layer to form a first gate mask; anisotropically etching the polysilicon layer to form a first polysilicon gate, wherein the first polysilicon gate has sidewalls with sloped profiles and the sloped profiles are used as masks during the ion implantation of the LDD structures to space the resultant LDD structures away from the edges of second polysilicon gates to be formed subsequently with substantially vertical profiles.
Warren B. Jackson - San Francisco CA Dave K. Biegelsen - Posto la Valley CA Lars Swartz - Sunnyvale CA Patrick Cheung - Castro Valley CA
Assignee:
Xerox Corporation - Stamford CT
International Classification:
F16D 3102
US Classification:
91 19, 60486, 91525, 92 89
Abstract:
A PC board actuator that emulates a muscle fiber includes a first pressure source, a second pressure source lower than the first source, at least one expansion chamber alternately communicating with the first and second pressure sources, first and second valves mounted with the PC board that opens and closes the chamber with respect to the first and second pressure sources, and an actuator member interacting with the expansion chamber to apply a force to the object. The actuator is preferably formed using planar batch technology and the valves preferably comprise electrically controllable flap valves mounted on the PC board. Alternatively, the actuator includes antagonistically arranged expansion chambers that operatively apply reciprocating forces to the object. In other embodiments, the actuator includes plural expansion chambers arranged in series or in parallel in order to increase the overall extent of attainable displacement or to amplify the force generated by the actuator.
Nicholas H. Tripsas - San Jose CA Matthew S. Buynoski - Palo Alto CA Suzette K. Pangrle - Cupertino CA Uzodinma Okoroanyanwu - Mountain View CA Angela T. Hui - Fremont CA Christopher F. Lyons - Fremont CA Ramkumar Subramanian - Sunnyvale CA Sergey D. Lopatin - Santa Clara CA Minh Van Ngo - Fremont CA Ashok M. Khathuria - San Jose CA Mark S. Chang - Los Altos CA Patrick K. Cheung - Sunnyvale CA Jane V. Oglesby - Mountain View CA
One aspect of the present invention relates to a method of fabricating a polymer memory device in a via. The method involves providing a semiconductor substrate having at least one metal-containing layer thereon, forming at least one copper contact in the metal-containing layer, forming at least one dielectric layer over the copper contact, forming at least one via in the dielectric layer to expose at least a portion of the copper contact, forming a polymer material in a lower portion of the via, and forming a top electrode material layer in an upper portion of the via.
Silicon Containing Material For Patterning Polymeric Memory Element
Ramkumar Subramanian - Sunnyvale CA Christopher F. Lyons - Fremont CA Matthew S. Buynoski - Palo Alto CA Patrick K. Cheung - Sunnyvale CA Angela T. Hui - Fremont CA Ashok M. Khathuria - San Jose CA Sergey D. Lopatin - Santa Clara CA Minh Van Ngo - Fremont CA Jane V. Oglesby - Mountain View CA Terence C. Tong - Sunnyvale CA James J. Xie - San Jose CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H01L 21336
US Classification:
438197, 438706
Abstract:
The present invention provides a method to fabricate an organic memory device, wherein the fabrication method includes forming a lower electrode, depositing a passive material over the surface of the lower electrode, applying an organic semiconductor material over the passive material, and operatively coupling the an upper electrode to the lower electrode through the organic semiconductor material and the passive material. Patterning of the organic semiconductor material is achieved by depositing a silicon-based resist over the organic semiconductor, irradiating portions of the silicon-based resist and patterning the silicon-based resist to remove the irradiated portions of the silicon-based resist. Thereafter, the exposed organic semiconductor can be patterned, and the non-irradiated silicon-based resist can be stripped to expose the organic semiconductor material that can be employed as a memory cell for single and multi-cell memory devices. A partitioning component can be integrated with the memory device to facilitate stacking memory devices and programming, reading, writing and erasing memory elements.
Pneumatic Actuator With Elastomeric Membrane And Low-Power Electrostatic Flap Valve Arrangement
David K. Biegelsen - Portola Valley CA Warren B. Jackson - San Francisco CA Lars-Erik Swartz - Sunnyvale CA Andrew A. Berlin - San Jose CA Patrick C. Cheung - Castro Valley CA
Assignee:
Xerox Corporation - Stamford CT
International Classification:
F15B 1108
US Classification:
91459, 91454
Abstract:
An actuator including a pneumatically distended elastomer membrane that is pressurized and depressurized using electrostatically actuated flap valves laminated onto a printed circuit board. The flap valves close only at zero pressure gradients and flows so that elevated closing and hold-off pressures are achieved. Fluid expelled from the elastomer membranes during collapse are vented through a wall of the actuator. An air jet object mover utilizes an array of the pneumatic actuators as valves to open and close air jet vents. A fiber optic micro-switch utilizes pneumatic actuators to position a mirror.
System And Method Of Forming A Passive Layer By A Cmp Process
Ramkumar Subramanian - Sunnyvale CA Jane V. Oglesby - Mountain View CA Minh Van Ngo - Fremont CA Mark S. Chang - Los Altos CA Sergey D. Lopatin - Santa Clara CA Angela T. Hui - Fremont CA Christopher F. Lyons - Fremont CA Patrick K. Cheung - Sunnyvale CA Ashok M. Khathuria - San Jose CA
The present invention provides systems and methods that facilitate formation of semiconductor devices via planarization processes. The present invention utilizes dishing effects that typically occur during a chemical mechanical planarization (CMP) process. A reducing CMP process is performed on a semiconductor device in order to form a passive layer instead of performing a first CMP, followed by a deposition and a second CMP to form a passive layer. The reducing CMP process utilizes a slurry that includes a reducing chemistry that forms the passive layer in a dish region of an electrode. Thus, the passive layer is formed in conjunction with the reducing CMP process utilized for forming the electrode.
Multi-Cell Organic Memory Element And Methods Of Operating And Fabricating
Sergey D. Lopatin - Santa Clara CA, US Mark S. Chang - Los Altos CA, US Minh Van Ngo - Fremont CA, US Patrick K. Cheung - Sunnyvale CA, US
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H01L029/76
US Classification:
257295, 257310
Abstract:
The present invention provides a multi-cell organic memory device that can operate as a non-volatile memory device having a plurality of multi-cell structures constructed within the memory device. A lower electrode can be formed, wherein one or more passive layers are formed on top of the lower electrode. An Inter Layer Dielectric (ILD) is formed above the passive layers and lower electrode, whereby a via or other type relief is created within the ILD and an organic semiconductor material is then utilized to partially fill the via above the passive layer. The portions of the via that are not filled with organic material are filled with dielectric material, thus forming a multi-dimensional memory structure above the passive layer or layers and the lower electrode. One or more top electrodes are then added above the memory structure, whereby distinctive memory cells are created within the organic portions of the memory structure and activated (e. g. , read/write) between the top electrodes and bottom electrode, respectively.
Memory Element Formation With Photosensitive Polymer Dielectric
Christopher F. Lyons - Fremont CA, US Terence C. Tong - Sunnyvale CA, US Patrick K. Cheung - Sunnyvale CA, US
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H01L021/00 H01L035/24
US Classification:
438 82, 257 40
Abstract:
A method of making organic memory devices containing organic memory cells made of two electrodes with a controllably conductive media between the two electrodes is disclosed. The organic memory devices are made using a patternable, photosensitive dielectric that facilitates formation of the memory cells and mitigates the necessity of using photoresists.
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