Patrick Wiley Curran

US Patent:

47047852, Nov 10, 1987

Filed:

Aug 1, 1986

Appl. No.:

6/893437

Inventors:

Patrick A. Curran - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21385
H01L 2140

US Classification:

437110

Abstract:

A process, and product made thereby, for bonding two wafers together to form a single wafer with a continuous interface, and for selectively burying a low impedance conductor in the wafer, by providing host and guest wafers having substantially the same crystal orientation and periodicity. A crystalline boundary n-semimetal is formed on the wafers, which are then brought into intimate contact. If desired, a unipolar conductor is fused to one of said wafers. Then, the wafers are exposed to an elevated temperature, or rapid thermal anneal, in an inert ambient, breaking up any native oxides and diffusing any excess oxygen into the wafer lattices. The guest wafer is then mechanically lapped back and chemically etched. A vertical cascode integrated half H-bridge motor driving circuit made in the guest and host wafers has a source transistor in the host wafer with with the wafer substrate forming the collector of the transistor, an isotype acceptor doped Ge. sub. x Si. sub. l-x /Si superlattice forming the base, and an overlying a monocrystalline silicon layer forming a compositional emitter, and with an n-semimetal boundary.

US Patent:

47176814, Jan 5, 1988

Filed:

May 19, 1986

Appl. No.:

6/864671

Inventors:

Patrick A. Curran - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21265
H01L 2972

US Classification:

437 31

Abstract:

A wafer process flow encompasses an arbitray repeated layered structure of heteroepitaxial layers of silicon based films with process control throughout the strata of chemical potential and recombination velocity, suitable for both high performance MOS and bipolar transistors with three dimensional transistor capability. A non-compensated doping technique preserves crystalline periodicity, as does the component delineation by means of anisotropic etching. The wafer is hermetic by means of the semi-insulation films polyimide, and the elimination of phosphorous doped silicon dioxide. A metallurgy system enables a high level integration.

US Patent:

47077212, Nov 17, 1987

Filed:

Feb 20, 1986

Appl. No.:

6/831379

Inventors:

Saw T. Ang - Garland TX
Patrick A. Curran - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2978
H01L 2904
H01L 2914
H01L 2946

US Classification:

357 54

Abstract:

A passivated dual dielectric gate system compatible with low temperature processing utilizes a dual dielectric system with a silicon dioxide dielectric film or layer at the monocrystalline substrate surface, or termination. The dual dielectric system includes a dielectric film at the substrate surface of thicknesses of from 200 to 1000. ANG. (or greater ). Respective layers of undoped amorphous silicon and titanium nitride overlie the top of the silicon dioxide and an aluminum gate metal layer overlies the titanium nitride layer. The structure can be patterned by selectively patterning photoresist and a dry or dry/wet etch processses. The structure is patterned and etched as desired. The system has enhanced surface mobilities due to lower oxide fixed charge density and smoother, more abrupt dielectric/monocrystalline interface region, is applicable to wide variety of MOSFET applications, and is inherently less electrostatic discharge (ESD) sensitive than conventional gate structures due to the distributed electric field.

US Patent:

47710136, Sep 13, 1988

Filed:

Aug 1, 1986

Appl. No.:

6/892681

Inventors:

Patrick A. Curran - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2704
H01L 2120

US Classification:

437 31

Abstract:

A three dimensional, bipolar wafer process for integrating high voltage, high power, analog, and digital circuitry, and structure formed thereby includes a wafer of non-compensated epitaxial strata on a heavily donor doped monocrystalline silicon substrate of crystal orientation, which is etched and with three dimensional transistors formed in it. Passivation for and contacts to said circuits are established, and the circuits are interconnected. The high voltage and high power transistors include transistors of an H-bridge circuit, including at least one set of cascode double heterojunction transistors, the analog transistors include a bipolar transistor, and the digital transistors include transistors of a I. sup. 2 L circuit. One method for constructing the wafer is by sequentially epitaxially depositing each strata in an UHV silicon-based MBE apparatus.

US Patent:

49011332, Feb 13, 1990

Filed:

Apr 2, 1986

Appl. No.:

6/847357

Inventors:

Patrick A. Curran - Plano TX
Susan R. Wilson - Richardson TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 4500
H01L 2934
H01L 2904

US Classification:

357 54

Abstract:

A film for hermetically passivating monocrystalline silicon includes sequential layers of undoped amorphous silicon, oxygen doped polycrystalline silicon, silicon rich oxynitride, and silicon nitride, and may be overlaid with an organic bulk dielectric such as polyimide. The inorganic film accurately sets the monocrystalline surface Fermi potential, independent of ambient electrical, mechanical, thermal, ionic, and moisture conditions. A method for depositing the amorphous silicon and the oxygen doped polycrystalline silicon layers of the film includes sequentially reacting monosilane in an inert carrier gas, such as helium or argon, and nitrous oxide. The layers are blended by varying the deposition temperature, the nitrous oxide flow rate, the monosilane flow rate, the monosilane dilution, and the inert carrier gas species. The layers are annealed to locally segregate the oxygen, to grow the grains to the proper size, and to set the final recombination velocity of the monocrystalline region.

US Patent:

47713267, Sep 13, 1988

Filed:

Jul 9, 1986

Appl. No.:

6/883876

Inventors:

Patrick A. Curran - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2972
H01L 2904
H01L 2954
H01L 2912

US Classification:

357 34

Abstract:

A heterojunction transistor has an acceptor doped superlattice base of sub-micron thickness, a composite emitter with a donor concentration adjacent the base, with a wider bandgap energy than the base, and with a low recombination velocity to minimize minority carrier diffusion and to set the divergence of emitter and base carrier velocities, and a collector configured like the emitter, permitting control and optimization of the cut-in voltage. The method for making the transistor includes forming the base, emitter, and collector by non-compensated, non-planar wafer processing techniques.

US Patent:

45463700, Oct 8, 1985

Filed:

Nov 21, 1984

Appl. No.:

6/674715

Inventors:

Patrick A. Curran - Garland TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2702

US Classification:

357 43

Abstract:

Monolithic integration of digital logic circuitry, precision control circuitry, and high voltage interface circuits on the same semiconductor chip is achieved, using various combinations selected from D-MOS, vertical NPN, lateral NPN, PNP, P-MOS, N-MOS, and J-FET components. Cathode driver circuits for a plasma display panel are integrated with this technology. Other applications include automotive and television circuits.

US Patent:

43251803, Apr 20, 1982

Filed:

Feb 15, 1979

Appl. No.:

6/012267

Inventors:

Patrick A. Curran - Garland TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2122

US Classification:

29571

Abstract:

Monolithic integration of digital logic circuitry, precision control circuitry, and high voltage interface circuits on the same semiconductor chip is achieved, including various combinations selected from D-MOS, vertical NPN, lateral NPN, PNP, P-MOS, N-MOS, and J-FET components. Cathode driver circuits for a plasma display panel are integrated with this technology. Other applications include automotive and television circuits.