Patrick G Weber

US Patent:

6495083, Dec 17, 2002

Filed:

May 17, 1999

Appl. No.:

09/312705

Inventors:

Patrick O. Weber - San Jose CA

Assignee:

Hestia Technologies, Inc. - Santa Clara CA

International Classification:

B29C 4502

US Classification:

26427215, 26427217, 29841, 425116, 425812

Abstract:

An integrated circuit chip package according to the present invention includes an integrated circuit chip mounted on a substrate by a plurality of solder bumps. A mold compound is used for underfilling air gaps between the chip and the substrate. The integrated circuit chip package is formed by placing the chip and substrate within a mold cavity and pressing a transfer mold compound into the mold cavity. Air spaces between the integrated circuit chip and the substrate are underfilled by the mold compound as it is pressed in between the integrated circuit chip and the substrate. Air is allowed to escape from between the chip and the substrate during the underfilling through a vent which extends through the substrate. The underfilling material may also be used to encapsulate the chip at the same time that underfilling is performed.

US Patent:

6560122, May 6, 2003

Filed:

Sep 28, 2001

Appl. No.:

09/967676

Inventors:

Patrick O. Weber - Mountain View CA

Assignee:

Hestia Technologies, Inc. - Santa Clara CA

International Classification:

H01L 2331

US Classification:

361783, 361760, 361770, 257667, 257737, 257738, 257778, 257787, 257789, 174260

Abstract:

An integrated circuit chip package according to the present invention includes an integrated circuit chip that is mounted on a substrate by a reflow process and by a plurality of solder bumps. At least one standoff is located between the circuit chip and the substrate to maintain a distance between the circuit chip and the substrate during the reflow process. A mold compound is used for underfilling air gaps between the chip and the substrate. The integrated circuit chip package is formed by placing the chip and substrate within a mold cavity and pressing a transfer mold compound into the mold cavity. Air spaces between the integrated circuit chip and the substrate are underfilled by the mold compound as it is pressed in between the integrated circuit chip, the standoffs and the substrate. Air is allowed to escape from between the chip and the substrate during the underfilling through a vent which extends through the substrate. The underfilling material may also be used to encapsulate the chip at the same time that underfilling is performed.

US Patent:

20100014234, Jan 21, 2010

Filed:

Jul 16, 2008

Appl. No.:

12/174518

Inventors:

Patrick O. Weber - Santa Clara CA, US

Assignee:

HESTIA TECHNOLOGIES, INC. - Santa Clara CA

International Classification:

H05K 7/18
B29D 11/00
H05K 3/20

US Classification:

36167906, 264 17, 29831

Abstract:

A method of manufacturing a display monitor, the method comprising: molding a pixel array frame having a plurality of pixel cavities and at least one pixel wall positioned adjacent to at least two pixel cavities, at least one of the pixel cavities having a light pit therein; molding a light diffusing material in the pixel cavities, wherein the light diffusing material does not enter the light pit; selecting a substrate having a top surface and a bottom surface, the substrate having a light source, such as a LED, on the top surface; coupling the bottom surface of the substrate to a printed circuit board configured to controllably operate the light source, wherein the light source is received within the light pit; and coupling the molded pixel array frame to the substrate.

US Patent:

20110017264, Jan 27, 2011

Filed:

Feb 19, 2009

Appl. No.:

12/389310

Inventors:

Patrick Weber - Santa Clara CA, US
Kevin Gibson - Redwood City CA, US
Ramon Rosal Reglos - San Ramon CA, US
Rick Briere - Santa Clara CA, US
Alelie Funcell - Fremont CA, US

Assignee:

Solaria Corporation - Fremont CA

International Classification:

H01L 31/052

US Classification:

136246

Abstract:

A photovoltaic device. The photovoltaic device includes a photovoltaic region including a surface region and characterized by a first thermal expansion constant. The surface region includes a first portion and a second portion, the second portion includes a first edge region and a second edge region. The photovoltaic device includes a concentrator element comprising substantially of a polymer material and being characterized by a second thermal expansion constant. The concentrator element includes an aperture region and an exit region. The photovoltaic device includes an elastomer material to couple the first portion of the surface region of the photovoltaic region to the exit region of the concentrator element, while the first edge region and the second edge region remain exposed. The first edge region and the second edge region allow for compensation by at least thermal expansion of the concentrator element for a change in temperature ranging from about −45 Degrees Celsius to about 95 Degrees Celsius to maintain the exit region to be optically coupled to the photovoltaic region.

US Patent:

60381361, Mar 14, 2000

Filed:

Oct 29, 1997

Appl. No.:

8/959927

Inventors:

Patrick O. Weber - San Jose CA

Assignee:

Hestia Technologies, Inc. - Sunnyvale CA

International Classification:

H01L 2331

US Classification:

361783

Abstract:

An integrated circuit chip package according to the present invention includes an integrated circuit chip mounted on a substrate by a plurality of solder bumps. A mold compound is used for underfilling air gaps between the chip and the substrate. The integrated circuit chip package is formed by placing the chip and substrate within a mold cavity and pressing a transfer mold compound into the mold cavity. Air spaces between the integrated circuit chip and the substrate are underfilled by the mold compound as it is pressed in between the integrated circuit chip and the substrate. Air is allowed to escape from between the chip and the substrate during the underfilling through a vent which extends through the substrate. The underfilling material may also be used to encapsulate the chip at the same time that underfilling is performed.

US Patent:

55976433, Jan 28, 1997

Filed:

Mar 13, 1995

Appl. No.:

8/402957

Inventors:

Patrick O. Weber - San Jose CA

Assignee:

Hestia Technologies, Inc. - Sunnyvale CA

International Classification:

B32B 900

US Classification:

428209

Abstract:

A multi-tier laminate substrate with an internal heat spreader and method for making a multi-tier laminate substrate with an internal heat spreader for electronic device packaging are provided wherein a spacing mechanism is used to protect the bond fingers of a trace on a lower tier of the laminated substrate when a milling bit is used to cut an opening above a die cavity in the multi-tier substrate,.

US Patent:

57282480, Mar 17, 1998

Filed:

Oct 17, 1996

Appl. No.:

8/731660

Inventors:

Patrick O. Weber - San Jose CA

Assignee:

Hestia Technologies, Inc. - Sunnyvale CA

International Classification:

B32B 3112
B32B 3118

US Classification:

156257

Abstract:

A multi-tier laminate substrate with an internal heat spreader and method for making a multi-tier laminate substrate with an internal heat spreader for electronic device packaging are provided wherein a spacing mechanism is used to protect the bond fingers of a trace on a lower tier of the laminated substrate when a milling bit is used to cut an opening above a die cavity in the multi-tier substrate.

US Patent:

56524633, Jul 29, 1997

Filed:

May 26, 1995

Appl. No.:

8/452024

Inventors:

Patrick O. Weber - San Jose CA
Michael A. Brueggeman - Mountain View CA

Assignee:

Hestia Technologies, Inc. - Sunnyvale CA

International Classification:

H01L 2310
H01L 2334

US Classification:

257706

Abstract:

A printed wiring board with either a pin grid array, a ball grid array, a land grid array, etc. of electrical contacts is prepared with a heat sink in the usual manner. A passage is provided either in the printed wiring board or in the heat sink so that during the transfer molding process, fluid molding compound passes latitudinally under the heat sink into a cavity below the heat sink to encapsulate the package.