Paul H Carlin

US Patent:

55594590, Sep 24, 1996

Filed:

Dec 29, 1994

Appl. No.:

8/366414

Inventors:

Paul R. Back - Groton MA
Paul R. Carlin - Bolton MA
Joseph M. Lamb - Hopedale MA

Assignee:

Stratus Computer, Inc. - Marlboro MA

International Classification:

H03K 1900

US Classification:

326 93

Abstract:

A clock signal generation arrangement for generating clocking signals for use in a fault-tolerant computer system generates a timing signal in response to a common clock signal. The clock signal generation arrangement comprises a system clock signal generator and a clock signal recovery circuit interconnected by a plurality of clock signal transfer lines. The system clock signal generator generates, in response to a common clock signal, a plurality of system clock signals preferably of uniform frequency and phase for transmission over a like plurality of clock signal transfer lines. The clock signal recovery circuit receives the system clock signals from the clock signal transfer lines and generates a unitary timing signal. The clock signal recovery circuit includes a voting circuit, a latch circuit and a latch control circuit. The voting circuit generates a voted clock signal having signal transitions that are generally aligned with transitions of a majority of the system clock signals.