Paul S Chan

US Patent:

6378026, Apr 23, 2002

Filed:

May 24, 1999

Appl. No.:

09/317502

Inventors:

Paul S. Chan - Cupertino CA
Raymond Chow - Saratoga CA
Joost Decupere - Zaventem, BE
Kim Lee - San Jose CA
Henry K. Wong - Cupertino CA

Assignee:

SIPEX Corporation - Billerica MA

International Classification:

G06F 1300

US Classification:

710300, 713323

Abstract:

A circuit and a method are presented which allow for the detection of an active communication device connected to the circuit. The circuit output signal can be used to reduce the power consumption of related equipment when communication is not detected for a predetermined period of time. The circuit includes a plurality of input terminals coupled to respective inactive detection blocks. The circuit also includes an accumulated delay block having delay circuits in serial electrical communication. Each inactive detection block provides a signal to a respective delay circuit that indicates whether the corresponding input terminal is connected to an active driver in the communication device. Each delay circuit provides a delayed output signal to a subsequent delay circuit. The accumulated delay block provides an output signal indicating the presence or absence of the communication device based on the activity at the input terminals over the predetermined period of time.

US Patent:

6611166, Aug 26, 2003

Filed:

Apr 23, 2001

Appl. No.:

09/840425

Inventors:

Paul S. Chan - Cupertino CA
Raymond Chow - Saratoga CA
Henry K. Wong - Cupertino CA

Assignee:

Sipex Corporation - Billerica MA

International Classification:

G05F 110

US Classification:

327536

Abstract:

Circuit and method for determining the presence of a load in a circuit including on a charge pump. The circuit monitors the state of a pump signal indicative of the operating status of the charge pump. The circuit generates a signal indicating the presence or absence of a load. The signal is used to deactivate features of an associated device, thereby reducing the power consumption and extending the life of the power supply (e. g. , battery) for the device.

US Patent:

7644221, Jan 5, 2010

Filed:

Apr 11, 2005

Appl. No.:

11/103319

Inventors:

Paul G. Chan - Oakland CA, US
Ricky C. Hetherington - Pleasanton CA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F 13/36

US Classification:

710315, 710306, 710314

Abstract:

A processor including an integrated system interface unit configured to manage multiple I/O interfaces and multiple protocols. A processor includes a plurality of processing cores, a cache comprising a plurality of banks, and a system interface unit coupled to the processing cores and the cache. The system interface unit includes an inbound unit configured to receive inbound transactions from a first I/O unit and a second I/O unit, and an outbound unit configured to convey outbound transactions to either the first I/O unit or the second I/O unit. Each of the first and second I/O units is configured to support different protocols. Prior to conveying transaction data to the system interface, the first I/O unit and second I/O units reformat transaction data to conform to a common format. The system interface receives and stores transaction data in either queues dedicated for cacheable transactions or queues dedicated for non-cacheable transactions. In addition, each of the I/O units may also indicate in the common format whether a given transaction is to be ordered with respect to other transactions.

US Patent:

7779307, Aug 17, 2010

Filed:

Feb 13, 2008

Appl. No.:

12/030857

Inventors:

John Gregory Favor - Scotts Valley CA, US
Paul G. Chan - Oakland CA, US
Graham Ricketson Murphy - Sunnyvale CA, US
Joseph Byron Rowlands - Santa Clara CA, US

Assignee:

Oracle America, Inc. - Redwood City CA

International Classification:

G06F 11/00

US Classification:

714 45, 714 38

Abstract:

An embodiment of the present invention includes a circuit for tracking memory operations with trace-based execution. Each trace includes a sequence of operations that includes zero or more of the memory operations. The memory operations being executed form a set of active memory operations that have a predefined program order among them and corresponding ordering constraints. At least some of the active memory operations access the memory in an execution order that is different from the program order. Checkpoint entries are associated with each trace. There is a one-to-one correspondence between checkpoint entries and memory operation ordering entries. Each checkpoint entry refers to a checkpoint location. Rollback requests cause the circuit to overwrite checkpoint entries associated with the corresponding trace.

US Patent:

7877630, Jan 25, 2011

Filed:

Feb 13, 2008

Appl. No.:

12/030852

Inventors:

John Gregory Favor - Scotts Valley CA, US
Paul G. Chan - Oakland CA, US
Graham Ricketson Murphy - Sunnyvale CA, US
Joseph Byron Rowlands - Santa Clara CA, US

Assignee:

Oracle America, Inc. - Redwood City CA

International Classification:

G06F 11/00

US Classification:

714 20, 714 45, 714 38

Abstract:

This invention includes a circuit for tracking memory operations with trace-based execution. Each trace includes a sequence of operations that includes zero or more of the memory operations. Traces execute atomically and become eligible for commitment after all the operations in the trace have executed. The memory operations being executed form a set of active memory operations that have a predefined program order among them and corresponding ordering constraints. At least some of the active memory operations access the memory in an execution order that is different from the program order. Checkpoint entries are associated with each trace. Each entry refers to a checkpoint location. Memory operation ordering entries correspond to each one of the active memory operations. Rollback requests result in overwriting the checkpoint locations associated with the selected trace as well as the checkpoint locations associated with traces that are younger than the selected trace.

US Patent:

7999357, Aug 16, 2011

Filed:

May 12, 2009

Appl. No.:

12/464805

Inventors:

Paul Chan - Cupertino CA, US

Assignee:

Semiconductor Components Industries, LLC - Phoenix AZ

International Classification:

H01L 29/06

US Classification:

257653, 361 54

Abstract:

The present invention advantageously provides a circular-arc shaped structure for forward biased steering diodes used in an ESD circuit, which circular arc shaped structure forward biases steering diodes effectively prevent concentration of an ESD pulse to one section of the p-n junction within the forward biased steering diode (or, alternatively viewed, evenly distributing stress along the entire p-n junction), thus increasing reliability of the ESD circuit, and also minimizing input capacitance as well as occupying a smaller area. The circular-arc shaped structure thus provides a mechanism to evenly distribute the current flow through the ESD steering diodes, and therefore avoids the disadvantage of a voltage gradient along the steering diode structure.

US Patent:

8010745, Aug 30, 2011

Filed:

Feb 13, 2008

Appl. No.:

12/030859

Inventors:

John Gregory Favor - Scotts Valley CA, US
Paul G. Chan - Oakland CA, US
Graham Ricketson Murphy - Sunnyvale CA, US
Joseph Byron Rowlands - Santa Clara CA, US

Assignee:

Oracle America, Inc. - Redwood City CA

International Classification:

G06F 9/00
G06F 13/00

US Classification:

711118, 711141, 711146, 711154, 712218, 712220

Abstract:

An embodiment of the present invention includes a circuit for tracking memory operations with trace-based execution. Each trace includes a sequence of operations that includes zero or more of the memory operations. The memory operations being executed form a set of active memory operations that have a predefined program order among them and corresponding ordering constraints. At least some of the active memory operations access the memory in an execution order that is different from the program order. Checkpoint entries are associated with each trace. When a memory operation attempts to update a cache line that may not be updated, the circuit attempts to upgrade the cache line. If this fails, a rollback request is generated that indicates the trace involved. The checkpoint locations associated with the indicated trace are overwritten along with those locations associated with all younger traces.

US Patent:

8019944, Sep 13, 2011

Filed:

Feb 13, 2008

Appl. No.:

12/030862

Inventors:

John Gregory Favor - Scotts Valley CA, US
Paul G. Chan - Oakland CA, US
Graham Ricketson Murphy - Sunnyvale CA, US
Joseph Byron Rowlands - Santa Clara CA, US

Assignee:

Oracle America, Inc. - Redwood City CA

International Classification:

G06F 9/00
G06F 13/00

US Classification:

711118, 711141, 711146, 711154, 712218, 712220

Abstract:

An embodiment of the present invention includes a circuit for tracking memory operations with trace-based execution. Each trace includes a sequence of operations that includes zero or more of the memory operations. The memory operations being executed form a set of active memory operations that have a predefined program order among them and corresponding ordering constraints. At least some of the active memory operations access the memory in an execution order that is different from the program order. Checkpoint entries are associated with each trace. Violations of the ordering constraints may be signaled too late to prevent an update of the cached data associated with the memory operations. A sub-circuit detects this condition and invalidates the checkpoint locations indicated by the checkpoint entries associated with the trace experiencing the violation and all younger traces.