Paul Suk Chang

US Patent:

8084308, Dec 27, 2011

Filed:

May 21, 2009

Appl. No.:

12/470128

Inventors:

Josephine Chang - Yorktown Heights NY, US
Paul Chang - Hopewell Junction NY, US
Michael A. Guillorn - Yorktown Heights NY, US
Jeffrey Sleight - Yorktown Heights NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/00
H01L 21/84
H01L 27/148
H01L 27/105

US Classification:

438151, 257 24, 257250, 257251, 257274, 257369, 257E21632, 257E21633, 257E21634, 257E21641, 257E27064, 977762, 977938

Abstract:

Nanowire-based devices are provided. In one aspect, a field-effect transistor (FET) inverter is provided. The FET inverter includes a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region, wherein the source and drain regions of one or more of the device layers are doped with an n-type dopant and the source and drain regions of one or more other of the device layers are doped with a p-type dopant; a gate common to each of the device layers surrounding the nanowire channels; a first contact to the source regions of the one or more device layers doped with an n-type dopant; a second contact to the source regions of the one or more device layers doped with a p-type dopant; and a third contact common to the drain regions of each of the device layers. Techniques for fabricating a FET inverter are also provided.

US Patent:

8216902, Jul 10, 2012

Filed:

Aug 6, 2009

Appl. No.:

12/536741

Inventors:

Josephine Chang - Yorktown Heights NY, US
Paul Chang - Hopewell Junction NY, US
Michael A. Guillorn - Yorktown Heights NY, US
Jeffrey Sleight - Yorktown Heights NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/8234

US Classification:

438275, 257E21645, 977938

Abstract:

Nanowire-based devices are provided. In one aspect, a SRAM cell includes at least one pair of pass gates and at least one pair of inverters formed adjacent to one another on a wafer. Each pass gate includes one or more device layers each having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region and a gate common to each of the pass gate device layers surrounding the nanowire channels. Each inverter includes a plurality of device layers each having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region and a gate common to each of the inverter device layers surrounding the nanowire channels.

US Patent:

8422273, Apr 16, 2013

Filed:

May 21, 2009

Appl. No.:

12/470159

Inventors:

Josephine Chang - Yorktown Heights NY, US
Paul Chang - Hopewell Junction NY, US
Michael A. Guillorn - Yorktown Heights NY, US
Jeffrey Sleight - Yorktown Heights NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11C 11/00

US Classification:

365151, 365157, 365164, 257 24, 977943

Abstract:

Nanowire-based field-effect transistors (FETs) and techniques for the fabrication thereof are provided. In one aspect, a FET is provided having a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region, wherein one or more of the device layers are configured to have a different threshold voltage from one or more other of the device layers; and a gate common to each of the device layers surrounding the nanowire channels.

US Patent:

20120109682, May 3, 2012

Filed:

Jun 16, 2010

Appl. No.:

13/378054

Inventors:

Paul Seltzer - Monsey NY, US
Paul J. Chang - Chicago IL, US

Assignee:

KONINKLIJKE PHILIPS ELECTRONICS N.V. - EINDHOVEN

International Classification:

G06Q 50/22

US Classification:

705 2

Abstract:

A system includes an orchestrator () with a processor () and a plurality of processing actors () in communication therewith. The processor () orchestrates closed-loop implementation of a healthcare imaging workflow plan by the plurality of processing actors ().

US Patent:

53676432, Nov 22, 1994

Filed:

Feb 6, 1991

Appl. No.:

7/651894

Inventors:

Paul Chang - Peekskill NY
Gary S. Delp - Yorktown Heights NY
Hanafy E. Meleis - Yorktown Heights NY
Rafael M. Montalvo - Yorktown Heights NY
David I. Seidman - New York NY
Ahmed N. Tantawy - Yorktown Heights NY
Dominick A. Zumbo - White Plains NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1300

US Classification:

395325

Abstract:

A generic high bandwidth adapter providing a unified architecture for data communications between buses, channels, processors, switch fabrics and/or communication networks. Data is carried by data stream packets of variable lengths, and each packet includes a header control information portion required by communication protocols used to mediate the information exchange, and normally a data portion for the data which is to be communicated. The generic high bandwidth adapter comprises a processor subsystem including a processor for processing the header control information portions of data packets. The processor has access to data packets stored in a packet memory which stores data packets arriving at four generic adapter input/output ports. The packet memory is segmented into a plurality of buffers, and each data packet is stored in one or more buffers as required by the length thereof. A generic adapter manager is provided for performing and synchronizing generic adapter management functions, including implementing data structures in the packet memory by organizing data packets in buffers, and organizing data packets into queues for processing by the processor subsystem or transfer to or from generic adapter input/output ports.

US Patent:

58357114, Nov 10, 1998

Filed:

Feb 1, 1995

Appl. No.:

8/382464

Inventors:

Paul Chang - Peekskill NY
Roch A. Guerin - Yorktown Heights NY
Abhay Kumar Parekh - White Plains NY
James Thomas Rayfield - Ridgefield CT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1300

US Classification:

39520013

Abstract:

A leaky bucket checker which combines synchronous updates with event driven asynchronous updates triggered by packet arrivals. A synchronous update is performed exactly as an event-driven update by assuming that a packet of length zero has arrived at the time of the update. These updates are performed in a round robin fashion on each connection. Therefore, assuming that one such update can be performed in each clock tick, the maximum bit representation of the last update time state variable can be limited to N bits for 2. sup. N total connections. Given the reduced processing and storage costs, a great number of network connections and leaky bucket checkers is possible.

US Patent:

56340150, May 27, 1997

Filed:

Oct 4, 1994

Appl. No.:

8/317894

Inventors:

Paul Chang - Peekskill NY
Gary S. Delp - Yorktown Heights NY
Hanafy E.-S. Meleis - Yorktown Heights NY
Rafael M. Montalvo - Yorktown Heights NY
David I. Seidman - New York NY
Ahmed N.-E.-D. Tantawy - Yorktown Heights NY
Dominick A. Zumbo - White Plains NY

Assignee:

IBM Corporation - Armonk NY

International Classification:

G06F 1300

US Classification:

395309

Abstract:

A generic high bandwidth adapter providing a unified architecture for data communications between buses, channels, processors, switch fabrics and/or communication networks. Data is carried by data stream packets of variable lengths, and each packet includes a header control information portion required by communication protocols used to mediate the information exchange, and normally a data portion for the data which is to be communicated. A packet memory stores data packets arriving at a plurality of generic adapter input/output ports. The packet memory is segmented into a plurality of buffers, and each data packet is stored in one or more buffers as required by the length thereof. A generic adapter manager is provided for performing and synchronizing generic adapter management functions, including implementing data structures in the packet memory by organizing data packets in buffers, and organizing data packets into queues for processing by the processor subsystem or transfer to or from generic adapter input/output ports. The generic adapter manager prepares future response to anticipated requests for communications services which are functions of the current requests for communication services, such as preparing a response for an anticipated request for a next buffer by a current request for a receipt of data.

US Patent:

54485657, Sep 5, 1995

Filed:

Nov 12, 1992

Appl. No.:

7/975236

Inventors:

Paul Chang - Peekskill NY
Joseph W. Coates - Cary NC
Edward H. C. Ku - Cary NC
Simin H. Sanaye - Raleigh NC

Assignee:

International Business Machines Corp. - Armonk NY

International Classification:

H04L 1246

US Classification:

370 8513

Abstract:

A multiport bridge includes a plurality of Bridge Port Frame Handler (BPFH) units coupled through a Source Routing bus and a Transparent Bridge Bus to a microcontroller, a Packet Memory and a Transparent Bridge Control Management System (TBCMS). Each Bridge Port Frame Handler unit receives Frames from its attached LAN, forwards selected portions of Source Routing Frames to other Bridge Port Frame Handler Units for further processing. Likewise, selected portions of Transparent Bridge Frames are forwarded to the TBCMS whereat routing information and signature information is extracted and returned to the forwarding BPFH unit for further processing.