Paul C Chang

US Patent:

7709910, May 4, 2010

Filed:

Apr 23, 2007

Appl. No.:

11/738666

Inventors:

William K. Henson - Beacon NY, US
Paul Chung-Muh Chang - Mahopac NY, US
Dureseti Chidambarrao - Weston CT, US
Ricardo A. Donaton - Cortlandt Manor NY, US
Yaocheng Liu - Elmsford NY, US
Shreesh Narasimha - Beacon NY, US
Amanda L. Tessier - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 29/78

US Classification:

257412, 257413, 257E21165

Abstract:

A semiconductor structure provides lower parasitic capacitance between the gate electrode and contact vias while providing substantially the same level of stress applied by a nitride liner as conventional MOSFETs by reducing the height of the gate electrode and maintaining substantially the same height for the gate spacer. The nitride liner contacts only the outer sidewalls of the gate spacer, while not contacting inner sidewalls, or only a small area of the inner sidewalls of the gate spacer, therefore applying substantially the same level of stress to the channel of the MOSFET as conventional MOSFETs. The volume surrounded by the gate spacer and located above the gate electrode is either filled with a low-k dielectric material or occupied by a cavity having a dielectric constant of substantially 1. The reduced height of the gate electrode and the low-k dielectric gate filler or the cavity reduces the parasitic capacitance.

US Patent:

7892945, Feb 22, 2011

Filed:

Aug 2, 2010

Appl. No.:

12/848582

Inventors:

Stephen W. Bedell - Wappingers Falls NY, US
Josephine B. Chang - Mahopac NY, US
Paul Chang - Mahopac NY, US
Michael A. Guillorn - Yorktown Heights NY, US
Jeffrey W. Sleight - Ridgefield CT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/76

US Classification:

438445, 438551, 438555, 438671

Abstract:

A semiconductor structure is provided that includes a plurality of vertically stacked and vertically spaced apart semiconductor nanowires (e. g. , a semiconductor nanowire mesh) located on a surface of a substrate. One end segment of each vertically stacked and vertically spaced apart semiconductor nanowires is connected to a source region and another end segment of each vertically stacked and vertically spaced apart semiconductor nanowires is connected to a drain region. A gate region including a gate dielectric and a gate conductor abuts the plurality of vertically stacked and vertically spaced apart semiconductor nanowires, and the source regions and the drain regions are self-aligned with the gate region.

US Patent:

7893492, Feb 22, 2011

Filed:

Feb 17, 2009

Appl. No.:

12/371943

Inventors:

Stephen W. Bedell - Wappingers Falls NY, US
Josephine B. Chang - Mahopac NY, US
Paul Chang - Mahopac NY, US
Michael A. Guillorn - Yorktown Heights NY, US
Jeffrey W. Sleight - Ridgefield CT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/02

US Classification:

257346, 257E23141, 977720, 977742, 977762, 977938

Abstract:

A semiconductor structure is provided that includes a plurality of vertically stacked and vertically spaced apart semiconductor nanowires (e. g. , a semiconductor nanowire mesh) located on a surface of a substrate. One end segment of each vertically stacked and vertically spaced apart semiconductor nanowires is connected to a source region and another end segment of each vertically stacked and vertically spaced apart semiconductor nanowires is connected to a drain region. A gate region including a gate dielectric and a gate conductor abuts the plurality of vertically stacked and vertically spaced apart semiconductor nanowires, and the source regions and the drain regions are self-aligned with the gate region.

US Patent:

8042070, Oct 18, 2011

Filed:

Oct 23, 2007

Appl. No.:

11/876853

Inventors:

James A. Culp - Newburgh NY, US
Paul Chang - Mahopac NY, US
Dureseti Chidambarrao - Weston CT, US
Praveen Elakkumanan - White Plains NY, US
Jason Hibbeler - Williston VT, US
Anda C. Mocuta - Lagrangeville NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50

US Classification:

716 56, 716 51, 716 54

Abstract:

Impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors. The impact of the design parameters are incorporated into parameters that measure predicted shift in mean on-current and mean off-current and parameters that measure predicted increase in deviations in the distribution of on-current and the off-current. Statistics may be taken at a cell level, a block level, or a chip level to optimize a chip design in a design phase, or to predict changes in parametric yield during manufacturing or after a depressed parametric yield is observed. Further, parametric yield and current level may be predicted region by region and compared with observed thermal emission to pinpoint any anomaly region in a chip to facilitate detection and correction in any mistakes in chip design.

US Patent:

8084308, Dec 27, 2011

Filed:

May 21, 2009

Appl. No.:

12/470128

Inventors:

Josephine Chang - Yorktown Heights NY, US
Paul Chang - Hopewell Junction NY, US
Michael A. Guillorn - Yorktown Heights NY, US
Jeffrey Sleight - Yorktown Heights NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/00
H01L 21/84
H01L 27/148
H01L 27/105

US Classification:

438151, 257 24, 257250, 257251, 257274, 257369, 257E21632, 257E21633, 257E21634, 257E21641, 257E27064, 977762, 977938

Abstract:

Nanowire-based devices are provided. In one aspect, a field-effect transistor (FET) inverter is provided. The FET inverter includes a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region, wherein the source and drain regions of one or more of the device layers are doped with an n-type dopant and the source and drain regions of one or more other of the device layers are doped with a p-type dopant; a gate common to each of the device layers surrounding the nanowire channels; a first contact to the source regions of the one or more device layers doped with an n-type dopant; a second contact to the source regions of the one or more device layers doped with a p-type dopant; and a third contact common to the drain regions of each of the device layers. Techniques for fabricating a FET inverter are also provided.

US Patent:

8216902, Jul 10, 2012

Filed:

Aug 6, 2009

Appl. No.:

12/536741

Inventors:

Josephine Chang - Yorktown Heights NY, US
Paul Chang - Hopewell Junction NY, US
Michael A. Guillorn - Yorktown Heights NY, US
Jeffrey Sleight - Yorktown Heights NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/8234

US Classification:

438275, 257E21645, 977938

Abstract:

Nanowire-based devices are provided. In one aspect, a SRAM cell includes at least one pair of pass gates and at least one pair of inverters formed adjacent to one another on a wafer. Each pass gate includes one or more device layers each having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region and a gate common to each of the pass gate device layers surrounding the nanowire channels. Each inverter includes a plurality of device layers each having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region and a gate common to each of the inverter device layers surrounding the nanowire channels.

US Patent:

8239790, Aug 7, 2012

Filed:

Aug 24, 2011

Appl. No.:

13/216362

Inventors:

James A. Culp - Newburgh NY, US
Paul Chang - Mahopac NY, US
Dureseti Chidambarrao - Weston CT, US
Praveen Elakkumanan - White Plains NY, US
Jason Hibbeler - Williston VT, US
Anda C. Mocuta - Lagrangeville NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50

US Classification:

716 56, 716 51, 716 54

Abstract:

Impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors. The impact of the design parameters are incorporated into parameters that measure predicted shift in mean on-current and mean off-current and parameters that measure predicted increase in deviations in the distribution of on-current and the off-current. Statistics may be taken at a cell level, a block level, or a chip level to optimize a chip design in a design phase, or to predict changes in parametric yield during manufacturing or after a depressed parametric yield is observed. Further, parametric yield and current level may be predicted region by region and compared with observed thermal emission to pinpoint any anomaly region in a chip to facilitate detection and correction in any mistakes in chip design.

US Patent:

8395220, Mar 12, 2013

Filed:

Mar 12, 2012

Appl. No.:

13/417829

Inventors:

Josephine Chang - Mahopac NY, US
Paul Chang - Mahopac NY, US
Michael A. Guillorn - Yorktown Heights NY, US
Jeffrey Sleight - Ridgefield CT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 27/088
B82Y 99/00

US Classification:

257368, 257E2706, 977938

Abstract:

Nanowire-based devices are provided. In one aspect, a SRAM cell includes at least one pair of pass gates and at least one pair of inverters formed adjacent to one another on a wafer. Each pass gate includes one or more device layers each having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region and a gate common to each of the pass gate device layers surrounding the nanowire channels. Each inverter includes a plurality of device layers each having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region and a gate common to each of the inverter device layers surrounding the nanowire channels.