Paul D Chang

US Patent:

6615864, Sep 9, 2003

Filed:

Jan 29, 2002

Appl. No.:

10/058199

Inventors:

Paul C. Chang - Tustin CA 92782

International Classification:

E04H 416

US Classification:

137521, 13762414, 137518, 15 17

Abstract:

A pool cleaner reed valve for a pulsating submersible swimming pool cleaner which has a valve body ( ) configured to fit into a pulsating valve enclosure. The body includes a rectangular inlet end ( ) and an round outlet end ( ) with a pair of fulcrum points ( ) and restricting boundaries ( ) for retaining and confining valve movements. A pair of opposed rigid valve plates ( ) are angularly juxtaposed within the valve inlet end contiguously engaging the fulcrum points and respective restricting boundaries such that each opposed blade rotates inwardly on the fulcrum point until the distal ends intimately engage as influenced by negative fluid pressure applied by a pool pump. A pair of torsion springs ( ) surround each restricting boundary and interface with each valve plate returning them to a parallel position when fluid pressure is terminated. A resilient sleeve ( ) is positioned on each spring for eliminating a metal to metal contact with the spring to the valve plate.

US Patent:

6743703, Jun 1, 2004

Filed:

Sep 9, 2002

Appl. No.:

10/238104

Inventors:

Vladimir Rodov - Redondo Beach CA
Paul Chang - Saratoga CA
Jianren Bao - Fullerton CA
Wayne Y. W. Hsueh - San Jose CA
Arthur Ching-Lang Chiang - Saratoga CA
Geeng-Chuan Chern - Cupertino CA

Assignee:

APD Semiconductor, Inc. - San Jose CA

International Classification:

H01L 2974

US Classification:

438527, 257341, 257495, 257653, 257401, 257133, 257155, 257355

Abstract:

A two-terminal power diode has improved reverse bias breakdown voltage and on resistance includes a semiconductor body having two opposing surfaces and a superjunction structure therebetween, the superjunction structure including a plurality of alternating P and N doped regions aligned generally perpendicular to the two surfaces. The P and N doped regions can be parallel stripes or a mesh with each region being surrounded by doped material of opposite conductivity type. A diode junction associated with one surface can be an anode region with a gate controlled channel region connecting the anode region to the superjunction structure. Alternatively, the diode junction can comprise a metal forming a Schottky junction with the one surface. The superjunction structure is within the cathode and spaced from the anode. The spacing can be varied during device fabrication.

US Patent:

6813274, Nov 2, 2004

Filed:

Mar 21, 2000

Appl. No.:

09/532341

Inventors:

Hiroshi Suzuki - Palo Alto CA
Paul Chang - San Jose CA
Sharat Prasad - San Jose CA
Chien Fang - Danville CA

Assignee:

Cisco Technology, Inc. - San Jose CA

International Classification:

H04L 1220

US Classification:

370412, 370386

Abstract:

A network switch and a method for data switching using a crossbar switch fabric with output port groups operating concurrently and independently that increases throughput and reduces scheduling complexity. The network switch includes a crossbar switch fabric, plurality of output port groups, and a plurality of input ports. The crossbar switch fabric includes a plurality of inputs and outputs. The plurality of output port groups operate concurrently and independently, and each output port group includes one or more output ports and is configured to receive a packet from one of the outputs of the crossbar switch and to send the packet to an output port. The plurality of input ports are coupled to an input of the crossbar switch fabric and configured to send packets to the crossbar switch fabric through the input of the crossbar switch fabric. Each input port includes a plurality of input buffer groups, and each input buffer group is assigned to send a packet for one of the output port groups such that there is a one-to-one correspondence between each of the input buffer groups and output port groups.

US Patent:

6891803, May 10, 2005

Filed:

Dec 18, 1998

Appl. No.:

09/215421

Inventors:

Paul Chang - Fremont CA, US
Tom Dang - San Jose CA, US
Chi Lin Wu - San Jose CA, US

Assignee:

Sunrise Telecom, Inc. - San Jose CA

International Classification:

H04L012/66

US Classification:

370252, 370248, 370251, 370247, 379 21, 379 1001, 348192, 714715

Abstract:

A test set includes at least one signal input port, a test circuitry, a processor, a user-input device, and a display. The test circuitry couples to and receives signals from the at least one signal input port. The test circuitry then generates test data corresponding to the received signals. The processor couples to and receives test data from the test circuitry and generates test results. The processor also couples to and receives commands from the user-input device. The processor further operatively couples to the graphical display that receives and displays the test results from the processor. In one embodiment, the test set is capable of performing line qualification and connectivity testing. A modem module can be used to facilitate connectivity testing. The modem module can be a plug-in module with a common interface to the test set.

US Patent:

6917595, Jul 12, 2005

Filed:

Oct 8, 2002

Appl. No.:

10/267191

Inventors:

Paul Chang - Fremont CA, US
Tom Dang - San Jose CA, US
Chi Lin Wu - San Jose CA, US

Assignee:

Sunrise Telecom, Inc. - San Jose CA

International Classification:

G01R031/08
G06F011/00
G08C015/00
H04J001/16
H04L001/00

US Classification:

370248, 370252, 370251, 370247, 379 2201, 379 2202, 379 2203, 714715

Abstract:

A test set includes at least one signal input port, a test circuitry, a processor, a user-input device, and a display. The test circuitry couples to and receives signals from the at least one signal input port. The test circuitry then generates test data corresponding to the received signals. The processor couples to and receives test data from the test circuitry and generates test results. The processor also couples to and receives commands from the user-input device. The processor further operatively couples to the graphical display that receives and displays the test results from the processor. In one embodiment, the test set is capable of performing line qualification and connectivity testing. A modem module can be used to facilitate connectivity testing. The modem module can be a plug-in module with a common interface to the test set.

US Patent:

6979861, Dec 27, 2005

Filed:

May 30, 2002

Appl. No.:

10/159558

Inventors:

Vladimir Rodov - Redondo Beach CA, US
Paul Chang - Saratoga CA, US
Gary M. Hurtz - Pleasanton CA, US
Geeng-Chuan Chern - Cupertino CA, US
Jianren Bao - Fullerton CA, US

Assignee:

APD Semiconductor, Inc. - San Jose CA

International Classification:

H01L029/76
H01L029/94
H01L031/062
H01L031/113
H01L031/119

US Classification:

257329, 257471, 438212

Abstract:

A power device having vertical current flow through a semiconductor body of one conductivity type from a top electrode to a bottom electrode includes at least one gate electrode overlying a gate insulator on a first surface of the body, a channel region of second conductivity type in the surface of the body underlying all of the gate electrode, a first doped region of the second conductivity type contiguous with the channel region and positioned deeper in the body than the channel region and under a peripheral region of the gate electrode, and a second doped source/drain region in the surface of the body abutting the channel region and adjacent to the gate electrode. When the gate is forward biased, an inversion region extends through the channel region and electrically connects the first electrode and the second electrode with a small Vnear to the area between adjacent P bodies being flooded with electrons and denuded of holes. Therefore, at any forward bias this area conducts as an N-type region. When the gate electrode is reverse biased, the long channel region underlying the full length of the gate electrode reduces reverse leakage current.

US Patent:

D553029, Oct 16, 2007

Filed:

Jul 20, 2005

Appl. No.:

29/234691

Inventors:

Paul Chang - Fremont CA, US

Assignee:

Sunrise Telecom Incorporated - San Jose CA

International Classification:

1004

US Classification:

D10 78

US Patent:

7340127, Mar 4, 2008

Filed:

Jan 31, 2005

Appl. No.:

11/048455

Inventors:

Paul Chang - Fremont CA, US

Assignee:

Sunrise Telecom Incorporated - San Jose CA

International Classification:

G02B 6/28

US Classification:

385 24

Abstract:

A method for optical spectrum analysis provides a tunable optical filter and scans a wavelength range of an optical signal that is larger than the free spectrum range of the tunable optical filter. The optical signal is filtered through the tunable optical filter. Separate multiple optical orders of the wavelengths scanned and filtered by the tunable optical filter are individually detected.