Paul C Chang

US Patent:

8084308, Dec 27, 2011

Filed:

May 21, 2009

Appl. No.:

12/470128

Inventors:

Josephine Chang - Yorktown Heights NY, US
Paul Chang - Hopewell Junction NY, US
Michael A. Guillorn - Yorktown Heights NY, US
Jeffrey Sleight - Yorktown Heights NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/00
H01L 21/84
H01L 27/148
H01L 27/105

US Classification:

438151, 257 24, 257250, 257251, 257274, 257369, 257E21632, 257E21633, 257E21634, 257E21641, 257E27064, 977762, 977938

Abstract:

Nanowire-based devices are provided. In one aspect, a field-effect transistor (FET) inverter is provided. The FET inverter includes a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region, wherein the source and drain regions of one or more of the device layers are doped with an n-type dopant and the source and drain regions of one or more other of the device layers are doped with a p-type dopant; a gate common to each of the device layers surrounding the nanowire channels; a first contact to the source regions of the one or more device layers doped with an n-type dopant; a second contact to the source regions of the one or more device layers doped with a p-type dopant; and a third contact common to the drain regions of each of the device layers. Techniques for fabricating a FET inverter are also provided.

US Patent:

8216902, Jul 10, 2012

Filed:

Aug 6, 2009

Appl. No.:

12/536741

Inventors:

Josephine Chang - Yorktown Heights NY, US
Paul Chang - Hopewell Junction NY, US
Michael A. Guillorn - Yorktown Heights NY, US
Jeffrey Sleight - Yorktown Heights NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/8234

US Classification:

438275, 257E21645, 977938

Abstract:

Nanowire-based devices are provided. In one aspect, a SRAM cell includes at least one pair of pass gates and at least one pair of inverters formed adjacent to one another on a wafer. Each pass gate includes one or more device layers each having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region and a gate common to each of the pass gate device layers surrounding the nanowire channels. Each inverter includes a plurality of device layers each having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region and a gate common to each of the inverter device layers surrounding the nanowire channels.

US Patent:

8268550, Sep 18, 2012

Filed:

Jun 26, 2009

Appl. No.:

12/459212

Inventors:

Paul Chang - Cambridge MA, US
Sejal Vyas - Cambridge MA, US

Assignee:

Massachusetts Institute of Technology - Cambridge MA

International Classification:

G01N 33/53

US Classification:

435 6, 436518

Abstract:

The invention provides nucleic acids encoding PARP fusion proteins, PARP fusion proteins, antibodies that bind to one or more of these PARP fusion proteins, and transgenic cells expressing one or more PARP fusion proteins. The invention also provides methods for identifying an agent as a specific PARP inhibitor or activator requiring contacting one or more PARP fusion proteins with a labeled nicotinamide adenine dinucleotide substrate and the agent and measuring the amount of labeled of ADP-ribose covalently attached to the one or more PARP fusion proteins. The invention also provides methods for identifying an agent that specifically binds to one or more PARP fusion proteins and methods for quantitating the level of one or more PARP proteins in a sample.

US Patent:

8395220, Mar 12, 2013

Filed:

Mar 12, 2012

Appl. No.:

13/417829

Inventors:

Josephine Chang - Mahopac NY, US
Paul Chang - Mahopac NY, US
Michael A. Guillorn - Yorktown Heights NY, US
Jeffrey Sleight - Ridgefield CT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 27/088
B82Y 99/00

US Classification:

257368, 257E2706, 977938

Abstract:

Nanowire-based devices are provided. In one aspect, a SRAM cell includes at least one pair of pass gates and at least one pair of inverters formed adjacent to one another on a wafer. Each pass gate includes one or more device layers each having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region and a gate common to each of the pass gate device layers surrounding the nanowire channels. Each inverter includes a plurality of device layers each having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region and a gate common to each of the inverter device layers surrounding the nanowire channels.

US Patent:

8422273, Apr 16, 2013

Filed:

May 21, 2009

Appl. No.:

12/470159

Inventors:

Josephine Chang - Yorktown Heights NY, US
Paul Chang - Hopewell Junction NY, US
Michael A. Guillorn - Yorktown Heights NY, US
Jeffrey Sleight - Yorktown Heights NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11C 11/00

US Classification:

365151, 365157, 365164, 257 24, 977943

Abstract:

Nanowire-based field-effect transistors (FETs) and techniques for the fabrication thereof are provided. In one aspect, a FET is provided having a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region, wherein one or more of the device layers are configured to have a different threshold voltage from one or more other of the device layers; and a gate common to each of the device layers surrounding the nanowire channels.

US Patent:

8435961, May 7, 2013

Filed:

Jun 23, 2010

Appl. No.:

12/821967

Inventors:

Paul Chang - Cambridge MA, US
Anthony Leung - Somerville MA, US
Phillip A. Sharp - Newton MA, US

Assignee:

Massachusetts Institute of Technology - Cambridge MA

International Classification:

A61K 31/70
A61K 31/00
A61K 39/395

US Classification:

514 44, 514 2, 4241301

Abstract:

The invention provides methods for increasing the activity of an inhibitory RNA (RNAi) in a subject requiring administering one or more poly-ADP-ribose polymerase (PARP) inhibitors and/or one or more PARG activators to the subject. The invention also provides methods for increasing the activity of an inhibitory RNA in a cell or cell population requiring contacting a cell or cell population with one or more PARP inhibitors and/or one or more PARG activators. The invention further provides compositions and kits containing one or more PARP inhibitors and/or one or more PARG activators.

US Patent:

8466451, Jun 18, 2013

Filed:

Dec 11, 2011

Appl. No.:

13/316515

Inventors:

Josephine Chang - Mahopac NY, US
Paul Chang - Mahopac NY, US
Michael A. Guillorn - Yorktown Heights NY, US
Jeffrey Sleight - Ridgefield CT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 29/06
H01L 31/00
H01L 27/105
H01L 27/148

US Classification:

257 24, 257250, 257251, 257274, 257369, 257E21641, 257E27064, 977938

Abstract:

A FET inverter is provided that includes a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels, wherein the source and drain regions of one or more of the device layers are doped with an n-type dopant and the source and drain regions of one or more other of the device layers are doped with a p-type dopant; a gate common to each of the device layers surrounding the nanowire channels; a first contact to the source regions of the one or more device layers doped with an n-type dopant; a second contact to the source regions of the one or more device layers doped with a p-type dopant; and a third contact common to the drain regions of each of the device layers. Techniques for fabricating a FET inverter are also provided.

US Patent:

8472239, Jun 25, 2013

Filed:

May 9, 2012

Appl. No.:

13/467126

Inventors:

Josephine Chang - Mahopac NY, US
Paul Chang - Mahopac NY, US
Michael A. Guillorn - Yorktown Heights NY, US
Jeffrey Sleight - Ridgefield CT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11C 11/00

US Classification:

365151, 365157, 365164, 257 24, 977943

Abstract:

Nanowire-based field-effect transistors (FETs) and techniques for the fabrication thereof are provided. In one aspect, a FET is provided having a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region, wherein one or more of the device layers are configured to have a different threshold voltage from one or more other of the device layers; and a gate common to each of the device layers surrounding the nanowire channels.