Paul P Chang

US Patent:

8084308, Dec 27, 2011

Filed:

May 21, 2009

Appl. No.:

12/470128

Inventors:

Josephine Chang - Yorktown Heights NY, US
Paul Chang - Hopewell Junction NY, US
Michael A. Guillorn - Yorktown Heights NY, US
Jeffrey Sleight - Yorktown Heights NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/00
H01L 21/84
H01L 27/148
H01L 27/105

US Classification:

438151, 257 24, 257250, 257251, 257274, 257369, 257E21632, 257E21633, 257E21634, 257E21641, 257E27064, 977762, 977938

Abstract:

Nanowire-based devices are provided. In one aspect, a field-effect transistor (FET) inverter is provided. The FET inverter includes a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region, wherein the source and drain regions of one or more of the device layers are doped with an n-type dopant and the source and drain regions of one or more other of the device layers are doped with a p-type dopant; a gate common to each of the device layers surrounding the nanowire channels; a first contact to the source regions of the one or more device layers doped with an n-type dopant; a second contact to the source regions of the one or more device layers doped with a p-type dopant; and a third contact common to the drain regions of each of the device layers. Techniques for fabricating a FET inverter are also provided.

US Patent:

8216902, Jul 10, 2012

Filed:

Aug 6, 2009

Appl. No.:

12/536741

Inventors:

Josephine Chang - Yorktown Heights NY, US
Paul Chang - Hopewell Junction NY, US
Michael A. Guillorn - Yorktown Heights NY, US
Jeffrey Sleight - Yorktown Heights NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/8234

US Classification:

438275, 257E21645, 977938

Abstract:

Nanowire-based devices are provided. In one aspect, a SRAM cell includes at least one pair of pass gates and at least one pair of inverters formed adjacent to one another on a wafer. Each pass gate includes one or more device layers each having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region and a gate common to each of the pass gate device layers surrounding the nanowire channels. Each inverter includes a plurality of device layers each having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region and a gate common to each of the inverter device layers surrounding the nanowire channels.

US Patent:

8422273, Apr 16, 2013

Filed:

May 21, 2009

Appl. No.:

12/470159

Inventors:

Josephine Chang - Yorktown Heights NY, US
Paul Chang - Hopewell Junction NY, US
Michael A. Guillorn - Yorktown Heights NY, US
Jeffrey Sleight - Yorktown Heights NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11C 11/00

US Classification:

365151, 365157, 365164, 257 24, 977943

Abstract:

Nanowire-based field-effect transistors (FETs) and techniques for the fabrication thereof are provided. In one aspect, a FET is provided having a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region, wherein one or more of the device layers are configured to have a different threshold voltage from one or more other of the device layers; and a gate common to each of the device layers surrounding the nanowire channels.

US Patent:

D686175, Jul 16, 2013

Filed:

Mar 20, 2012

Appl. No.:

29/416224

Inventors:

Alexander I. Gurary - Bridgewater NJ, US
Keng Moy - Basking Ridge NJ, US
Paul Chang - Easton PA, US

Assignee:

Veeco Instruments Inc. - Plainview NY

International Classification:

1303

US Classification:

D13182

US Patent:

D695242, Dec 10, 2013

Filed:

Mar 20, 2012

Appl. No.:

29/416244

Inventors:

Alexander I. Gurary - Bridgewater NJ, US
Keng Moy - Basking Ridge NJ, US
Paul Chang - Easton PA, US

Assignee:

Veeco Instruments Inc. - Plainview NY

International Classification:

1303

US Classification:

D13182

US Patent:

20020004500, Jan 10, 2002

Filed:

Mar 28, 2001

Appl. No.:

09/819549

Inventors:

Richard Reeves - Pennington NJ, US
Robert Wolf - Newton PA, US
Paul Chang - Doylestown PA, US

International Classification:

A61K031/55

US Classification:

514/212030

Abstract:

Vasopeptidase inhibitors, especially omapatrilat, are useful in treating isolated systolic hypertension. The vasopeptidase inhibitor may be used in combination with other pharmaceutically active agents.

US Patent:

20120109682, May 3, 2012

Filed:

Jun 16, 2010

Appl. No.:

13/378054

Inventors:

Paul Seltzer - Monsey NY, US
Paul J. Chang - Chicago IL, US

Assignee:

KONINKLIJKE PHILIPS ELECTRONICS N.V. - EINDHOVEN

International Classification:

G06Q 50/22

US Classification:

705 2

Abstract:

A system includes an orchestrator () with a processor () and a plurality of processing actors () in communication therewith. The processor () orchestrates closed-loop implementation of a healthcare imaging workflow plan by the plurality of processing actors ().

US Patent:

53676432, Nov 22, 1994

Filed:

Feb 6, 1991

Appl. No.:

7/651894

Inventors:

Paul Chang - Peekskill NY
Gary S. Delp - Yorktown Heights NY
Hanafy E. Meleis - Yorktown Heights NY
Rafael M. Montalvo - Yorktown Heights NY
David I. Seidman - New York NY
Ahmed N. Tantawy - Yorktown Heights NY
Dominick A. Zumbo - White Plains NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1300

US Classification:

395325

Abstract:

A generic high bandwidth adapter providing a unified architecture for data communications between buses, channels, processors, switch fabrics and/or communication networks. Data is carried by data stream packets of variable lengths, and each packet includes a header control information portion required by communication protocols used to mediate the information exchange, and normally a data portion for the data which is to be communicated. The generic high bandwidth adapter comprises a processor subsystem including a processor for processing the header control information portions of data packets. The processor has access to data packets stored in a packet memory which stores data packets arriving at four generic adapter input/output ports. The packet memory is segmented into a plurality of buffers, and each data packet is stored in one or more buffers as required by the length thereof. A generic adapter manager is provided for performing and synchronizing generic adapter management functions, including implementing data structures in the packet memory by organizing data packets in buffers, and organizing data packets into queues for processing by the processor subsystem or transfer to or from generic adapter input/output ports.