Paul Rene Estrada

US Patent:

59371900, Aug 10, 1999

Filed:

Apr 3, 1995

Appl. No.:

8/417147

Inventors:

Brent Gregory - Sunnyvale CA
Trinanjan Chatterjee - Sunnyvale CA
Jing C. Lin - Sunnyvale CA
Srinivas Raghvendra - Sunnyvale CA
Emil Girczyc - Los Altos CA
Paul Estrada - Mountain View CA
Andrew Seawright - Cupertino CA

Assignee:

Synopsys, Inc. - Mountain View CA

International Classification:

G06F 945

US Classification:

395704

Abstract:

A digital circuit is synthesized from a text description of a digital system. During synthesis, a parse tree with parse nodes is constructed and retained. The relationship between the parse nodes and the circuit elements synthesized from those parse nodes is retained. Using that relationship, analysis results associated with circuit elements can be related to the text that generated those circuit elements. In particular, the analysis results can be used to set the display characteristics, such as font or size, of the text associated with those results.

US Patent:

61321095, Oct 17, 2000

Filed:

Jun 3, 1994

Appl. No.:

8/253470

Inventors:

Brent Gregory - Sunnyvale CA
Trinanjan Chatterjee - Sunnyvale CA
Jing C. Lin - Sunnyvale CA
Srinivas Raghvendra - Sunnyvale CA
Emil Girczyc - Los Altos CA
Paul Estrada - Mountain View CA
Andrew Seawright - Cupertino CA

Assignee:

Synopsys, Inc. - Mountain View CA

International Classification:

G06F 9445
G06F 945
G06F 1500

US Classification:

395704

Abstract:

This invention provides a method for displaying circuit analysis results corresponding to parts of the circuit near the portion of the hardware description language (HDL) specification that generated that part of the circuit. The invention also includes a method for using probe statements in the HDL specification to mark additional points in the initial circuit that should not be eliminated during optimization. This improves the ability to display circuit analysis results near the appropriate part of the HDL specification.