Paul A Gray

US Patent:

20120284622, Nov 8, 2012

Filed:

May 6, 2011

Appl. No.:

13/102458

Inventors:

Ryan L. Avery - San Francisco CA, US
Stephen Crocker - Tyngsboro MA, US
Paul J. Gray - Cambridge MA, US

International Classification:

G06F 3/048

US Classification:

715719, 715716

Abstract:

Methods and systems for providing media editing capability to a user of a mobile device in communication with a video or an audio media editing system. The methods involve receiving at the mobile device information specifying a current user context of the media editing system and automatically activating functionality on the mobile device that corresponds to the current editing context. The functionality may be a subset of the editing system controls, controls associated with a plug-in software module, or new controls or control modalities enabled by the form factor and input modes featured on the mobile device. The functionality of the mobile device may be updated as the editing context changes, or temporarily frozen to enable multi-user work flows, with each user using a different editing function.

US Patent:

41298632, Dec 12, 1978

Filed:

Oct 3, 1977

Appl. No.:

5/838908

Inventors:

Paul R. Gray - Orinda CA
James L. McCreary - Red Bank NJ
David A. Hodges - Berkeley CA

Assignee:

Regents of the University of California - Berkeley CA

International Classification:

H03K 1302

US Classification:

340347AD

Abstract:

An array of binary weighed capacitors, an additional capacitor having a capacitance value equivalent to that of the least of the binary weighted capacitors, a voltage comparator, switches for interconnecting the capacitors with certain predetermined voltage levels and the comparator, and a sequencing circuit are included. One side of all of the capacitors is connected to one input terminal on the comparator and the other side has applied thereto the signal to be quantized. Switch sequencing combines divided portions of a reference voltage with the signal to be quantized for presentation to the input of the comparator which thereby provides a serial digit output connected to the sequencing circuit. In this fashion, a linear conversion between an analog and a digital signal is made by the sequencing circuit. A nonlinear converter between digital and analog signal presentation is also disclosed.

US Patent:

42008638, Apr 29, 1980

Filed:

Dec 11, 1978

Appl. No.:

5/968590

Inventors:

David A. Hodges - Berkeley CA
Paul R. Gray - Orinda CA
James L. McCreary - Santa Clara CA

Assignee:

The Regents of the University of California - CA

International Classification:

H03K 1302

US Classification:

340347AD

Abstract:

An array of binary weighted capacitors, an additional capacitor having a capacitance value equivalent to that of the least of the binary weighted capacitors, a voltage comparator, switches for interconnecting the capacitors with certain predetermined voltage levels and the comparator, and a sequencing circuit are included. One side of all of the capacitors is connected to one input terminal on the comparator and the other side has applied thereto the signal to be quantized. Switch sequencing combines divided portions of a reference voltage with the signal to be quantized for presentation to the input of the comparator which thereby provides a serial digit output connected to the sequencing circuit. In this fashion, a linear conversion between an analog and a digital signal is made by the sequencing circuit. A nonlinear converter between digital and analog signal presentation is also disclosed.

US Patent:

41715098, Oct 16, 1979

Filed:

Jan 19, 1978

Appl. No.:

5/870620

Inventors:

Mark L. Stephens - Campbell CA
Paul R. Gray - Orinda CA

Assignee:

Signetics Corporation - Sunnyvale CA

International Classification:

G01L 118

US Classification:

323 75C

Abstract:

A bridge circuit for a measurement bridge of the type using four impedance arms provides an output referenced to ground which is a function of the impedances in the respective arms. The bridge circuit includes an impedance bridge comprising first, second, third and fourth impedance arms connected in series loop with first, second, third and fourth bridge terminals serially defined at the connections between the respective arms. A source of constant current is connected between the first terminal and ground. A driver is connected to bridge terminals other than the output terminal. The driver is responsive to bridge terminal signals to provide a bridge output which is a function of the impedances in the respective arms.

US Patent:

48976113, Jan 30, 1990

Filed:

Oct 28, 1988

Appl. No.:

7/264401

Inventors:

Carlos A. Laber - Los Altos CA
Paul R. Gray - Orinda CA

Assignee:

Micro Linear Corporation - San Jose CA

International Classification:

H03F 138
H03F 316

US Classification:

330253

Abstract:

This invention is for a transconductance amplifier. The amplifier has an amplifier input and an amplifier output with an amplifier output impedance. An input stage of the amplifier has a first transconductance. An intermediate state is coupled to the amplifier output through positive feedback. The intermediate stage has a second transconductance and an intermediate stage output having an intermediate output impedance. The gain of the amplifier is a function of the first transconductance times the second transconductance times the amplifier output impedance times the intermediate output impedance.

US Patent:

41684400, Sep 18, 1979

Filed:

Jan 12, 1978

Appl. No.:

5/868976

Inventors:

Paul R. Gray - Orinda CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03H 1100

US Classification:

307233R

Abstract:

An active filter employing a plurality of integrators which may be fabricated as a metal-oxide-semiconductor (MOS) integrated circuit is described. S-plane zeros are obtained without additional active devices when compared to prior art filters without such zeros. The zeros result from resistive coupling between the integrators. Resistance ratios and capacitance ratios primarily determine the filter's characteristics rather than the absolute value of these elements. This permits the filter to be readily fabricated with existing MOS technology.

US Patent:

50271164, Jun 25, 1991

Filed:

Feb 24, 1987

Appl. No.:

7/018019

Inventors:

Michael Armstrong - San Jose CA
Paul R. Gray - Orinda CA

Assignee:

Micro Linear Corporation - San Jose CA

International Classification:

H03M 110

US Classification:

341120

Abstract:

A self calibrating algorithmic analog-to-digital converter is disclosed for which the gain of the conversion loop is precisely adjusted and controlled by an array of switched capacitors such control being stored in a latch. The offset of the gain stage is reduced by reducing the amount of charge injected from the gate of the input zeroing MOS switch.

US Patent:

52834832, Feb 1, 1994

Filed:

Jan 27, 1993

Appl. No.:

8/009886

Inventors:

Carlos A. Laber - Los Altos CA
Paul R. Gray - Orinda CA

Assignee:

Micro Linear Corporation - San Jose CA

International Classification:

H03K 1716

US Classification:

307520

Abstract:

A fast parasitic-insensitive continuous-time filter and equalizer integrated circuit that uses an active integrator is described. Circuit techniques for excess-phase cancellation, and for setting the corner-frequency of the filter and equalizer are also described. These techniques result in a filter and equalizer chip with performance independent of process, supply, and temperature without employing phase-lock loops. This 20MHz 6th order Bessel filter and 2nd order equalizer operate from 5V, and generate only 0. 24% (-52 dB) of total harmonic distortion when processing 2 Vp-p differential output signals. The device is optimized to limit high-frequency noise and to amplitude equalize the data pulses in hard disk read-channel systems. The device supports data rates of up to 36 Mbps, and is built in a 1. 5. mu. /4 GHz BiCMOS technology.