Paul H Jordan

US Patent:

6336182, Jan 1, 2002

Filed:

Mar 5, 1999

Appl. No.:

09/263668

Inventors:

John Edward Derrick - Round Rock TX
Lee Evan Eisen - Austin TX
Paul Joseph Jordan - Austin TX
Robert William Hay - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 900

US Classification:

712204, 712 23

Abstract:

A method and system for aligning internal operations (IOPs) for dispatch are disclosed. The method and system comprise conditionally asserting a predecode based on a particular dispatch slot that an instruction is going to be placed. The method and system further include using the information related to the predecode to expand an instruction into at least one dummy operation and an IOP operation whenever the instruction would not be supported in the particular dispatch slot.

US Patent:

6629170, Sep 30, 2003

Filed:

Nov 8, 1999

Appl. No.:

09/436110

Inventors:

Joel Roger Davidson - Austin TX
Michael Stephen Floyd - Leander TX
Paul Joseph Jordan - Austin TX
Judith E. K. Laurens - Bastrop TX
Alexander Erik Mericas - Austin TX
Kevin F. Reick - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1300

US Classification:

710100, 710262, 710305, 711 31, 711130, 712218, 714 37, 714 47, 702176, 702181, 702182, 702186

Abstract:

A multi-stage byte lane selectable bus. In a preferred embodiment, the bus in performance monitor mode includes a plurality of byte lanes and a selection mechanism. The selection mechanism acquires, from a plurality of signals, a subset of those signals, which are desired to be monitored, and places this subset of signals on the byte lanes that are input to the PMU. The number of the plurality of signals that potentially may be monitored is greater than the number of byte lanes and is also greater than the number of PMU counters.

US Patent:

6658534, Dec 2, 2003

Filed:

Mar 31, 1998

Appl. No.:

09/052247

Inventors:

Steven Wayne White - Austin TX
Hung Qui Le - Austin TX
Kurt Alan Feiste - Austin TX
Paul Joseph Jordan - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1200

US Classification:

711137, 711125, 712207, 712237

Abstract:

The mechanism to reduce instruction cache miss penalties by initiating an early cache line prefetch is implemented. The mechanism provides for an early prefetch of a next succeeding cache line before an instruction cache miss is detected during a fetch which causes an instruction cache miss. The prefetch is initiated when it is guaranteed that instructions in the subsequent cache line will be referenced. This occurs when the current instruction is either a non-branch instruction, so instructions will execute sequentially, or if the current instruction is a branch instruction, but the branch forward is sufficiently short. If the current instruction is a branch, but the branch forward is to the next sequential cache line, a prefetch of the next sequential cache line may be performed. In this way, cache miss latencies may be reduced without generating cache pollution due to the prefetch of cache lines which are subsequently unreferenced.

US Patent:

6701484, Mar 2, 2004

Filed:

Aug 11, 2000

Appl. No.:

09/635456

Inventors:

Paul Joseph Jordan - Austin TX
Peter Juergen Klim - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1100

US Classification:

714801, 714718

Abstract:

A register for a computer processor removes the parity check from the critical path of CPU operation, and delays the parity check to the next immediate clock cycle. The register has a memory array, and read and write decoders for accessing the memory array using select lines. The select lines are also connected to read and write address latches which are used to index a parity bit array. When a value is written to, or read from, the memory array, its corresponding parity bit is calculated and either stored in the parity bit array (for a write operation), or compared to an existing parity bit array entry (for a read operation). The parity check is performed on a copy of the value contained in a read data latch or a write data latch. Each data latch has an input connected to a respective read or write port of the memory array. The latches delay the parity check by only one cycle.

US Patent:

6785847, Aug 31, 2004

Filed:

Aug 3, 2000

Appl. No.:

09/631714

Inventors:

Paul J. Jordan - Austin TX
Peter J. Klim - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1100

US Classification:

714 37, 714 42, 714 49, 714 54, 714819, 712221

Abstract:

Aspects for soft error detection for a superscalar microprocessor are described. The aspects include a first pipeline, the first pipeline including a first arithmetic logic unit, ALU, comparator and a first general purpose register, GPR, for storing first data, and a second pipeline, the second pipeline including a second GPR and a second ALU comparator, the second GPR for storing second data, the second data being a copy of the first data. A detection system utilizes one of the first and second ALU comparators to perform a comparison of the second data with the first data during an idle state of the first and second pipelines.

US Patent:

6857083, Feb 15, 2005

Filed:

Dec 18, 2000

Appl. No.:

09/740530

Inventors:

Michael S. Floyd - Leander TX, US
Paul J. Jordan - Austin TX, US
Larry S. Leitner - Cedar Park TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F011/00

US Classification:

714 30, 712227

Abstract:

A processor core for transitioning a debugging unit between a plurality of operating states generates trace data as it processes operating signals of an instruction stream. The processor core provides a trigger event signal to the debugging unit in response to a trigger instruction signal within the instruction stream that is representative of triggering instruction for transitions debugging unit to one of (1) a base operating state, (2) a dynamic storage operating state or (3) a static storage operating state. Concurrently or alternatively, the processor core can provide the trigger event signal to the debugging unit as a function of generated trigger data in response to additional operational instructions within the instruction stream.

US Patent:

7178005, Feb 13, 2007

Filed:

Jun 30, 2004

Appl. No.:

10/881225

Inventors:

Paul J. Jordan - Austin TX, US
Ashley N. Saulsbury - Los Gatos CA, US
John G. Johnson - San Jose CA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F 12/00

US Classification:

711217, 711219

Abstract:

A method and mechanism for managing timers in a multithreaded processing system. A storage device stores a plurality of count values corresponding to a plurality of timers. A read address generator is coupled to convey a read address to the storage device. The read address generator is configured to maintain and increment a first counter. In response to determining the counter does not equal a predetermined value, the mechanism conveys a first read address for use in accessing a count value in the storage device. In response to determining the count equals the predetermined value, the mechanism conveys a second read address for use in accessing a count value in the storage device. The predetermined value is utilized to repeat accesses to a given count value a predetermined number of times.

US Patent:

7343474, Mar 11, 2008

Filed:

Jun 30, 2004

Appl. No.:

10/881616

Inventors:

Paul J. Jordan - Austin TX, US
Robert T. Golla - Round Rock TX, US
Jama I. Barreh - Austin TX, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F 9/30

US Classification:

712214

Abstract:

In one embodiment, a processor comprises a plurality of pipeline stages and a first circuit operable at a first pipeline stage of the plurality of pipeline stages. The first circuit is configured to maintain a plurality of program counters (PCs), each of which corresponds to one of a plurality of threads that the processor is configured to have concurrently in process with respect to the plurality of pipeline stages. The first circuit is configured to provide a first PC to a second pipeline stage of the plurality of pipeline stages. The first PC is derived from one of the plurality of PCs that corresponds to a first thread of the plurality of threads, and a first instruction entering the second pipeline stage is from the first thread.