Paul K Jordan

US Patent:

6976205, Dec 13, 2005

Filed:

Sep 21, 2001

Appl. No.:

09/962724

Inventors:

Syrus Ziai - Sunnyvale CA, US
Paul Jordan - Austin TX, US
Craig Robson - Sunnyvale CA, US
Ryan Donohue - Mountain View CA, US
Fong Pong - Mountain View CA, US

Assignee:

Syrus Ziai - Sunnyvale CA

International Classification:

H03M013/09

US Classification:

714807

Abstract:

A method is described that involves performing a checksum calculation on a section of data within an inbound packet before the section of data is first stored into a system memory. Another method is described that involves moving a section of data within an outbound packet from a system memory to an offload memory. Then, removing the section of data from the offload memory; and performing a checksum calculation on the section of data. An apparatus is described that includes a central processing unit that is communicatively coupled with a network processing offload unit, wherein the network processing offload unit calculates a checksum upon a section of data located within an inbound packet, and calculates a checksum upon a section of data within an outbound packet.

US Patent:

7274706, Sep 25, 2007

Filed:

Apr 24, 2001

Appl. No.:

09/841943

Inventors:

Tung Nguyen - Cupertino CA, US
Fong Pong - Mountain View CA, US
Paul Jordan - Austin TX, US
Syrus Ziai - Sunnyvale CA, US
Al Chang - Yorktown Heights NY, US
Greg Grohoski - Austin TX, US

Assignee:

Syrus Ziai - Sunnyvale CA

International Classification:

H04L 12/28
H04L 12/56
H04L 12/66
H04J 3/16
H04J 3/22

US Classification:

370419, 370463, 370469

Abstract:

Methods and systems for processing data communicated over a network. In one aspect, an exemplary embodiment includes processing a first group of network packets in a first processor which executes a first network protocol stack, where the first group of network packets are communicated through a first network interface port, and processing a second group of network packets in a second processor which executes a second network protocol stack, where the second group of network packets is communicated through the first network interface port. Other methods and systems are also described.

US Patent:

7350053, Mar 25, 2008

Filed:

Jan 11, 2005

Appl. No.:

11/034345

Inventors:

Rabin A. Sugumar - Sunnyvale CA, US
Robert T. Golla - Austin TX, US
Paul J. Jordan - Austin TX, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F 9/26
G06F 9/34
G06F 12/00

US Classification:

711207, 711205, 711208, 711221

Abstract:

A method to communicate data is disclosed which includes communicating a virtual address to a translation lookaside buffer (TLB) and translating the virtual address to a physical address of a computer memory. The method also includes loading the physical address translated by the TLB into a register within a processor and transmitting the data from the physical address to a destination computing device.

US Patent:

7779238, Aug 17, 2010

Filed:

Oct 30, 2006

Appl. No.:

11/589492

Inventors:

Nicolai Kosche - San Francisco CA, US
Gregory F. Grohoski - Bee Cave TX, US
Paul J. Jordan - Austin TX, US

Assignee:

Oracle America, Inc. - Redwood City CA

International Classification:

G06F 11/30

US Classification:

712227, 712244, 717130

Abstract:

A system and method for precisely identifying an instruction causing a performance-related event is disclosed. The instruction may be detected while in a pipeline stage of a microprocessor preceding a writeback stage and the microprocessor's architectural state may not be updated until after information identifying the instruction is captured. The instruction may be flushed from the pipeline, along with other instructions from the same thread. A hardware trap may be taken when the instruction is detected and/or when an event counter overflows or is within a given range of overflowing. A software trap handler may capture and/or log information identifying the instruction, such as one or more extended address elements, before returning control and initiating a retry of the instruction. The captured and/or logged information may be stored in an event space database usable by a data space profiler to identify performance bottlenecks in the application containing the instruction.

US Patent:

8099586, Jan 17, 2012

Filed:

Dec 30, 2008

Appl. No.:

12/346349

Inventors:

Yuan C. Chou - Los Gatos CA, US
Robert T. Golla - Round Rock TX, US
Mark A. Luttrell - Cedar Park TX, US
Paul J. Jordan - Austin TX, US
Manish Shah - Austin TX, US

Assignee:

Oracle America, Inc. - Redwood City CA

International Classification:

G06F 9/00

US Classification:

712233, 712239

Abstract:

A system and method for reducing branch misprediction penalty. In response to detecting a mispredicted branch instruction, circuitry within a microprocessor identifies a predetermined condition prior to retirement of the branch instruction. Upon identifying this condition, the entire corresponding pipeline is flushed prior to retirement of the branch instruction, and instruction fetch is started at a corresponding address of an oldest instruction in the pipeline immediately prior to the flushing of the pipeline. The correct outcome is stored prior to the pipeline flush. In order to distinguish the mispredicted branch from other instructions, identification information may be stored alongside the correct outcome. One example of the predetermined condition being satisfied is in response to a timer reaching a predetermined threshold value, wherein the timer begins incrementing in response to the mispredicted branch detection and resets at retirement of the mispredicted branch.

US Patent:

20120246437, Sep 27, 2012

Filed:

Mar 22, 2011

Appl. No.:

13/069337

Inventors:

Zoran Radovic - San Jose CA, US
Graham Ricketson Murphy - Sunnyvale CA, US
Paul J. Jordan - Austin TX, US
John G. Johnson - San Jose CA, US

Assignee:

ORACLE INTERNATIONAL CORPORATION - Redwood City CA

International Classification:

G06F 12/10
G06F 12/02

US Classification:

711170, 711206, 711200, 711E12002, 711E12058

Abstract:

The disclosed embodiments provide a system that uses unused bits in a memory pointer. During operation, the system determines a set of address bits in a address space that will not be needed for addressing purposes during program operation. Subsequently, the system stores data associated with the memory pointer in this set of address bits. The system masks this set of address bits when using the memory pointer to access the memory address associated with the memory pointer. Storing additional data in unused pointer bits can reduce the number of memory accesses for a program and improve program performance and/or reliability.

US Patent:

20130297910, Nov 7, 2013

Filed:

May 3, 2012

Appl. No.:

13/463319

Inventors:

Jared C. Smolens - San Jose CA, US
Robert T. Golla - Round Rock TX, US
Mark A. Luttrell - Cedar Park TX, US
Paul J. Jordan - Austin TX, US

International Classification:

G06F 9/30
G06F 9/38

US Classification:

712205, 712216, 712E09016, 712E09028

Abstract:

Systems and methods for efficient thread arbitration in a threaded processor with dynamic resource allocation. A processor includes a resource shared by multiple threads. The resource includes entries which may be allocated for use by any thread. Control logic detects long latency instructions. Long latency instructions have a latency greater than a given threshold. One example is a load instruction that has a read-after-write (RAW) data dependency on a store instruction that misses a last-level data cache. The long latency instruction or an immediately younger instruction is selected for replay for an associated thread. A pipeline flush and replay for the associated thread begins with the selected instruction. Instructions younger than the long latency instruction are held at a given pipeline stage until the long latency instruction completes. During replay, this hold prevents resources from being allocated to the associated thread while the long latency instruction is being serviced.

US Patent:

20140075163, Mar 13, 2014

Filed:

Sep 7, 2012

Appl. No.:

13/607175

Inventors:

Paul N. Loewenstein - Palo Alto CA, US
Mark A. Luttrell - Cedar Park TX, US
Paul J. Jordan - Austin TX, US

International Classification:

G06F 9/312

US Classification:

712225, 712E09033

Abstract:

Techniques are disclosed relating to suspending execution of a processor thread while monitoring for a write to a specified memory location. An execution subsystem may be configured to perform a load instruction that causes the processor to retrieve data from a specified memory location and atomically begin monitoring for a write to the specified location. The load instruction may be a load-monitor instruction. The execution subsystem may be further configured to perform a wait instruction that causes the processor to suspend execution of a processor thread during at least a portion of an interval specified by the wait instruction and to resume execution of the processor thread at the end of the interval. The wait instruction may be a monitor-wait instruction. The processor may be further configured to resume execution of the processor thread in response to detecting a write to a memory location specified by a previous monitor instruction.