Paul Christopher Moore

US Patent:

6356327, Mar 12, 2002

Filed:

Mar 29, 1999

Appl. No.:

09/277901

Inventors:

Paul McKay Moore - San Bruno CA

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

G02F 11343

US Classification:

349139, 430311

Abstract:

A pixel cell array for a silicon light valve positions a reflective metal surface underneath inter-pixel regions. This underlying reflective metal surface reflects incident light, thereby preventing absorption of light in inter-pixel regions that can disturb charge stored in underlying capacitors or cause dark lines to appear between electrodes. The underlying reflective metal surface can be formed as a plurality of discrete, floating, electrically-isolated structures. Alternatively, the underlying reflective metal surface can formed as a plurality of discrete structures linked to adjacent pixel electrodes through via structures. The underlying reflective metal surface can also be designed as a continuous grid including a contact for receiving an applied bias.

US Patent:

6452647, Sep 17, 2002

Filed:

Feb 28, 2001

Appl. No.:

09/795801

Inventors:

Paul McKay Moore - San Bruno CA

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

G02F 1136

US Classification:

349 38, 349139

Abstract:

A receiver receives a signal transmitted by a time-division multi-access method that divides one frame into a plurality of communication slots in conducting communication. In this receiver, a detection circuit detects whether a received RF signal is stronger than a predetermined level. The received RF signal is demodulated by a demodulation circuit. An oscillation circuit generates a clock that is used to decode the data obtained by demodulation. The data obtained by demodulation is stored in a memory in synchronism with a clock reproduced from the received signal, and is then retrieved from the memory in synchronism with the clock generated by the oscillation circuit. This eliminates jitters. After jitter elimination, the data is decoded by a processing circuit. The writing/reading operation against the memory is initialized in accordance with a result output from the detection circuit.

US Patent:

6452652, Sep 17, 2002

Filed:

Jun 12, 1998

Appl. No.:

09/096914

Inventors:

Paul M. Moore - Burlingame CA

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

G02F 113

US Classification:

349110, 349137

Abstract:

A light absorbing thin film stack is placed in an upper interconnect level of a pixel cell of an LCD light valve to prevent transmission of light from the small gap between adjacent pixel electrodes into the silicon substrate. The light absorbing thin film stack includes a surface layer combination formed over a highly absorbing backstopping layer. Incident light is absorbed by the backstopping layer. Light reflected by the surface layer combination and/or the backstopping layer is extinguished by destructive interference. This destructive interference is generated by a change in the phase angle caused by the differing optical properties of the various layers of the light absorbing thin film stack.

US Patent:

6577362, Jun 10, 2003

Filed:

May 24, 1999

Appl. No.:

09/317496

Inventors:

Paul McKay Moore - San Bruno CA

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

G02F 11335

US Classification:

349114, 349113, 349 38, 349 39

Abstract:

A pixel cell for a silicon LC light valve features a plurality of transparent electrically conducting pixel electrodes formed over a grounded reflective metal backplane. Dielectric material intervenes between the transparent electrodes and the grounded reflective backplane. This dielectric material, alone or in combination with the transparent electrode, creates a reflectance enhancing coating generating constructive interference of light reflected by the underlying backplane. The dielectric material also serves as the dielectric of an additional capacitive component having the active electrode and the grounded reflective metal backplane as plates. This architecture enhances the storage capacitance of the pixel cell, lowering sensitivity of the pixel to current leakage and reducing the pixel cell surface area. This pixel architecture also reduces the appearance of dark lines attributable to absorption of light in inter-pixel regions.

US Patent:

6701478, Mar 2, 2004

Filed:

Dec 22, 2000

Appl. No.:

09/746999

Inventors:

Changyong Yang - San Jose CA
Paul B. Moore - Woodside CA

Assignee:

Nortel Networks Limited - St. Laurent

International Classification:

H03M 1305

US Classification:

714757, 714758, 714776, 714781

Abstract:

The present invention relates to a system and method to generate a CRC (Cyclic Redundancy Check) value using a plurality of CRC generators operating in parallel. The system includes a switching module operatively coupled to a parallel data bus. The switching module generates and places a packet cycle on the parallel data bus to transmit a data packet and packet modification commands to modify the data packet. The system further includes a bridging module operatively coupled to the parallel data bus. The bridging module modifies the data packet in accordance to the packet modification commands, and generates a Cyclic Redundancy Check (CRC) value to reflect modifications made to the data packet. The bridging module utilizes a plurality of CRC generators operating in parallel to generate the CRC value quickly and efficiently.

US Patent:

6725315, Apr 20, 2004

Filed:

Dec 22, 2000

Appl. No.:

09/747239

Inventors:

Changyong Yang - San Jose CA
Paul B. Moore - Woodside CA

Assignee:

Nortel Networks Limited - St. Laurent

International Classification:

G06F 1336

US Classification:

710306, 710310, 710315, 711147, 711111, 711138, 711154

Abstract:

The present invention relates to a system and method to efficiently move data from one data bus to another data bus in a network switch. The method includes generating a packet cycle on a first data bus. The method also includes generating a control data cycle on a second data bus. The method further includes processing the packet cycle on the first data bus after processing the control data cycle on the second data bus.

US Patent:

6916692, Jul 12, 2005

Filed:

Feb 28, 2001

Appl. No.:

09/797054

Inventors:

Paul McKay Moore - San Bruno CA, US

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H01L021/84

US Classification:

438156, 438 30

Abstract:

The present invention provides a pixel array and a process flow for forming an array of pixel cells that features pixel electrodes having overlapping edges. This overlapping pixel configuration precludes absorption of light in inter-pixel regions that could give rise to the appearance of dark lines between bright reflective pixel electrodes. This pixel arrangement also prevents the disruption of charge stored in underlying capacitor structures due to the penetration of incident light through inter-pixel regions into the underlying substrate.

US Patent:

6949784, Sep 27, 2005

Filed:

Nov 1, 2002

Appl. No.:

10/285977

Inventors:

Paul M. Moore - San Mateo CA, US

Assignee:

Micrel, Inc. - San Jose CA

International Classification:

H01L027/108
G11C016/04

US Classification:

257300, 257318, 3651851, 365184

Abstract:

A memory device includes a coupling capacitor and a field-effect transistor. The coupling capacitor is formed from (1) a first dopant region in a second dopant region on a substrate, (2) a gate dielectric atop the first dopant region, and (3) a first gate conductor atop the gate dielectric. The coupling capacitor has the first gate conductor coupled to a second gate conductor of the field-effect transistor. A voltage can be applied to the second dopant region to isolate the coupling capacitor from the substrate by reverse biasing a PN junction formed between the first dopant region and the second dopant region.