Paul C Pierce

US Patent:

7058750, Jun 6, 2006

Filed:

May 10, 2000

Appl. No.:

09/569100

Inventors:

Linda J. Rankin - Beaverton OR, US
Paul R. Pierce - Portland OR, US
Gregory E. Dermer - Portland OR, US
Wen-Hann Wang - Portland OR, US
Kai Cheng - Portland OR, US
Richard H. Hofsheier - Banks OR, US
Nitin Y. Borkar - Beaverton OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 13/00

US Classification:

710317, 710310

Abstract:

A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.

US Patent:

7343442, Mar 11, 2008

Filed:

Jun 6, 2006

Appl. No.:

11/422542

Inventors:

Linda J. Rankin - Beaverton OR, US
Paul R. Pierce - Portland OR, US
Gregory E. Dermer - Portland OR, US
Wen-Hann Wang - Portland OR, US
Kai Cheng - Portland OR, US
Richard H. Hofsheier - Banks OR, US
Nitin Y. Borkar - Beaverton OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 13/00

US Classification:

710317, 710310

Abstract:

A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.

US Patent:

7603508, Oct 13, 2009

Filed:

Jan 14, 2008

Appl. No.:

12/013595

Inventors:

Linda J. Rankin - Beaverton OR, US
Paul R. Pierce - Portland OR, US
Gregory E. Dermer - Portland OR, US
Wen-Hann Wang - Portland OR, US
Kai Cheng - Portland OR, US
Richard H. Hofsheier - Banks OR, US
Nitin Y. Borkar - Beaverton OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 13/00

US Classification:

710317, 710310

Abstract:

A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.

US Patent:

7930464, Apr 19, 2011

Filed:

Aug 28, 2009

Appl. No.:

12/549491

Inventors:

Linda J. Rankin - Portland OR, US
Paul R. Pierce - Portland OR, US
Gregory E. Dermer - Portland OR, US
Wen-Hann Wang - Portland OR, US
Kai Cheng - Portland OR, US
Richard H. Hofsheier - Banks OR, US
Nitin Y. Borkar - Beaverton OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 13/00

US Classification:

710317, 710306

Abstract:

A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.

US Patent:

8255605, Aug 28, 2012

Filed:

Mar 30, 2011

Appl. No.:

13/076041

Inventors:

Linda J. Rankin - Portland OR, US
Paul R. Pierce - Portland OR, US
Gregory E. Dermer - Portland OR, US
Wen-Hann Wang - Shanghai, CN
Kai Cheng - Portland OR, US
Richard H Hofsheier - Banks OR, US
Nitin Y. Borkar - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 13/00

US Classification:

710306

Abstract:

A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BICS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.

US Patent:

20020178019, Nov 28, 2002

Filed:

Jun 29, 2001

Appl. No.:

09/895557

Inventors:

Andrew Anderson - Hillsboro OR, US
Paul Pierce - Portland OR, US
Uttam Sengupta - Portland OR, US
Ticky Thakkar - Portland OR, US
Kit Tham - Portland OR, US
Nick Wade - Portland OR, US
Trevor Pering - Mountain View CA, US
Steve Bennett - Hillsboro OR, US
Lee Hirsch - Cupertino CA, US
Scott Robinson - Portland OR, US

International Classification:

G06F017/60

US Classification:

705/001000

Abstract:

A method and apparatus for taking action in response to an event without contacting at least one person if the level of importance of the event to a first person meets or exceeds one threshold, but is below or only meeting another threshold.

US Patent:

20020178022, Nov 28, 2002

Filed:

Dec 31, 2001

Appl. No.:

10/039960

Inventors:

Andrew Anderson - Hillsboro OR, US
Steve Bennett - Hillsboro OR, US
Trevor Pering - Mountain View CA, US
Paul Pierce - Portland OR, US
Scott Robinson - Portland OR, US
Uttam Sengupta - Portland OR, US
Ticky Thakkar - Portland OR, US
Kit Tham - Portland OR, US
Nick Wade - Portland OR, US

International Classification:

G06F017/60

US Classification:

705/001000

Abstract:

A method and apparatus for attempting to contact at least one person in response to an event if the level of importance of the event to a first person meets or exceeds one threshold.

US Patent:

20020178226, Nov 28, 2002

Filed:

May 24, 2001

Appl. No.:

09/865919

Inventors:

Andrew Anderson - Hillsboro OR, US
Paul Pierce - Portland OR, US
Uttam Sengupta - Portland OR, US
Ticky Thakkar - Portland OR, US
Kit Tham - Portland OR, US
Nick Wade - Portland OR, US
Trevor Pering - Mountain View CA, US
Steve Bennett - Hillsboro OR, US
Lee Hirsch - Cupertino CA, US

International Classification:

G06F015/16
G06F009/46

US Classification:

709/206000, 709/318000

Abstract:

A method and apparatus for escalating messages to a user concerning events of importance to the user comprising receiving information concerning an event, evaluating its importance to the user, and if the event is determined to be important enough for the user to be contacted, selecting a first way of contacting the user and using that first way to do so, waiting for a period of time for the user to respond, and if the user does not respond, selecting a second way of contacting the user and using that second way to do so.