Paul E Platt

US Patent:

48779784, Oct 31, 1989

Filed:

Sep 19, 1988

Appl. No.:

7/246634

Inventors:

Paul E. Platt - Starkville MS

Assignee:

Cypress Semiconductor - San Jose CA

International Classification:

H03K 19017
H03K 19096
H03K 1704
H03K 17687

US Classification:

307473

Abstract:

The invention pertains to an output buffer circuit capable of switching from the off state to the on state, and from the on state to the off state, without generating significant noise. The circuit includes an MOS inverter circuit having a first node adapted to be connected to one terminal of a power supply and a second node adapted to be connected to the other node, and having an input for receiving an input signal and an output for providing an output signal adapted to be connected to an output transistor. The circuit also has a first MOS transistor of one polarity type and one mode having its source-drain circuit coupled in series with the first node of the inverter circuit, and a second MOS transistor opposite in either polarity type or mode from the first MOS transistor, having its source-drain circuit coupled in series with the other node of the inverter circuit. A first reference voltage is supplied to the gate of the first MOS transistor and a second mirrored reference voltage is supplied to the gate of the second MOS transistor. These reference voltages are capable of generating a stable current over normal variations in operating and processing conditions, whereby the rise and fall times of the output signal from the inverter circuit are precisely controlled, irrespective of normal changes in operating or processing conditions of the MOS transistor in the circuit, thereby reducing noise when the output transistor connected to the output is turned on or off.

US Patent:

61148407, Sep 5, 2000

Filed:

Sep 17, 1998

Appl. No.:

9/154995

Inventors:

Michael Francis Farrell - Atlanta GA
Paul Edwin Platt - Duluth GA

Assignee:

Integrated Device Technology, Inc. - Santa Clara CA

International Classification:

H03K 1704

US Classification:

322374

Abstract:

Signal transfer devices enable multiple processors to act as drivers or receivers of signals which can transition from an invalid state to a valid state and then return to the invalid state in one clock cycle. The preferred signal transfer device includes a bus line, a plurality of bus drivers electrically connected to the bus line for initiating wired-OR signal transitions and at least one self-timed booster circuit electrically connected to the bus line. The self-timed booster circuit includes a first field effect transistor electrically connected in series between the bus line and a first reference potential and a second field effect transistor electrically connected in series between the bus line and a second reference potential. A timing circuit is also provided as a plurality of inverters which are electrically coupled in series. The timing circuit, which has an input electrically coupled to the bus line, performs a boolean inversion of the signals on the bus line after a first delay.

US Patent:

49186647, Apr 17, 1990

Filed:

Jan 18, 1989

Appl. No.:

7/298472

Inventors:

Paul E. Platt - Starkville MS

Assignee:

Cypress Semiconductor - San Jose CA

International Classification:

G11C 800

US Classification:

36523005

Abstract:

The invention relates to a random access memory having more than one port capable of accessing the same storage addresses. It provides a system for protection of data integrity at each port. First and second ports are capable of providing first and second address transition signals to enable data storage in a single memory address. A comparator is coupled to the first and second ports (1) for detecting address transitions indicating that the second port is addressing a particular memory address coincidentally when the first port also is addressing the same memory address, and (2) for generating a busy output signal for that address in the event of such coincidence. A transition detection circuit is used to detect the transition resulting from the removal of the busy output signal from the comparator and for providing a busy removal output signal equivalent to an address detection signal in the event of such detection. Finally, the busy removal output signal is combined with the transition detection signals, whereby the data from the second port may be written into the single memory address irrespective of whether the second port itself provides an address transition signal at that time.