Paul R Reed

Address:

14250 Canton Spg Ln, Houston, TX 77044

VIN:

WBAVC93547KZ70793

Make:

BMW

Model:

3 SE

Year:

2007

US Patent:

48189006, Apr 4, 1989

Filed:

Jun 1, 1982

Appl. No.:

6/383637

Inventors:

Jeffrey M. Klass - Rosenberg TX
Paul A. Reed - Houston TX
Isam Rimawi - Houston TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03K 17687

US Classification:

307450

Abstract:

An electrically programmable memory array having rows and columns of floating gate type memory cells employs alternate output lines and ground lines between the columns of cells, providing a virtual ground arrangement. A row is selected by one part of an address input, and a column selected by another part. An output line on one side of the selected column is activated, and a ground line on the other side. A differential sense amplifier is responsive to the voltage on the selected output line and a reference voltage. The number of transistors needed in the decoder for the row select function is greatly reduced by employing predecoders which perform a 1-of-4 select for each pair of address bits, then using one of these select outputs to activate N multiplexers, and all the others as inputs to a decoder with N outputs to the multiplexers.

US Patent:

42813972, Jul 28, 1981

Filed:

Oct 29, 1979

Appl. No.:

6/088789

Inventors:

Joseph H. Neal - Missouri City TX
Paul A. Reed - Houston TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11C 1140

US Classification:

365189

Abstract:

An array of rows and columns of memory cells of the virtual ground type employs a cell layout which has one column line per column instead of requiring extra lines for ground. Half of the column lines are used as outputs and half as ground. One output line and one ground line are selected by improved decode circuitry. The cell array is of a continuous web type wherein metal-to-silicon contacts are shared by four adjacent cells.

US Patent:

43441548, Aug 10, 1982

Filed:

Feb 4, 1980

Appl. No.:

6/118288

Inventors:

Jeffrey M. Klaas - Rosenberg TX
Paul A. Reed - Houston TX
Isam Rimawi - Houston TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11C 702

US Classification:

365194

Abstract:

An electrically programmable memory array having rows and columns of floating gate type memory cells employs alternate output lines and ground lines between the columns of cells, providing a virtual ground arrangement. A row is selected by one part of an address input, and a column selected by another part. An output line on one side of the selected column is activated, and a ground line on the other side. A differential sense amplifier is responsive to the voltage on the selected output line and a reference voltage. In a programming mode of operation, the application of high voltages to the row and column lines is controlled to prevent programming voltage from reaching a selected column until after all transistors in a row are turned on by programming voltage on a row line. This prevents unwanted programming conditions.

US Patent:

43143628, Feb 2, 1982

Filed:

Feb 4, 1980

Appl. No.:

6/118287

Inventors:

Jeffrey M. Klaas - Rosenberg TX
Paul A. Reed - Houston TX
Isam Rimawi - Houston TX

Assignee:

Texas Instruments, Incorporated - Dallas TX

International Classification:

G11C 700

US Classification:

365227

Abstract:

An electrically programmable memory array having rows and columns of floating gate type memory cells employs alternate output lines and ground lines between the columns of cells, providing a virtual ground arrangement. A row is selected by one part of an address input, and a column selected by another part. An output line on one side of the selected column is activated, and a ground line on the other side. A differential sense amplifier is responsive to the voltage on the selected output line and a reference voltage. A power down mode of operation is provided in which current flow in various circuits of the device is greatly reduced. To speed up access time in exiting from power down, the reference voltage input to the sense amplifier is shifted during power down then when exiting returns to its operating value according to a time constant.

US Patent:

43874479, Jun 7, 1983

Filed:

Feb 4, 1980

Appl. No.:

6/118349

Inventors:

Jeffrey M. Klaas - Rosenberg TX
Paul A. Reed - Houston TX
Isam Rimawi - Houston TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11C 1140
G11C 700

US Classification:

365203

Abstract:

An electrically programmable memory array having rows and columns of floating gate type memory cells employs alternate output lines and ground lines between the columns of cells, providing a virtual ground arrangement. A row is selected by one part of an address input, and a column selected by another part. An output line on one side of the selected column is activated, and a ground line on the other side. A differential sense amplifier is responsive to the voltage on the selected output line and a reference voltage. To speed up the access time of the memory, the ground select is implemented and applied first, then the output of the ground select is used to generate the column select. In this manner, the biasing sequence for the array can begin before the decode of the column select has been completed.