Paul Wynn Rohwer

US Patent:

6496876, Dec 17, 2002

Filed:

Dec 21, 1998

Appl. No.:

09/217781

Inventors:

Paul W. Rohwer - Nampa ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G06F 300

US Classification:

710 3, 714 54, 714763, 711103, 711170

Abstract:

Dysfunctional storage locations in a memory device may be demarcated by identifying a first and second dysfunctional storage location in the memory device, and storing a first tag before the first identified storage location, the first tag indicating a storage location immediately after the second identified storage location. A second tag may be used to demarcate functional storage locations by identify a functional storage location, and storing a second tag at the identified functional storage location, the second tag indicating a storage location immediately preceding the first identified dysfunctional storage location.

US Patent:

60095369, Dec 28, 1999

Filed:

Sep 20, 1996

Appl. No.:

8/716947

Inventors:

Paul W. Rohwer - Nampa ID

Assignee:

Micron Electronics, Inc. - Nampa ID

International Classification:

G06F 1100

US Classification:

714 8

Abstract:

A new method for masking off failing memory locations on a Single In-line Memory Module (SIMM) involves reading out identification (ID) codes fused in individual DRAMs. The ID codes are used to index stored fail maps taken from the DRAMs prior to their assembly onto a SIMM. After all failing locations of all of the DRAMs located on a single SIMM are determined, the SIMM is then programmed to re-route these locations to auxiliary memory located on the SIMM.

US Patent:

59130202, Jun 15, 1999

Filed:

Aug 22, 1997

Appl. No.:

8/918604

Inventors:

Paul W. Rohwer - Nampa ID

Assignee:

Micron Electronics, Inc. - Nampa ID

International Classification:

G06F 1100

US Classification:

39518206

Abstract:

A new method for masking off failing memory locations on a Single In-line Memory Module (SIMM) involves reading out identification (ID) codes fused in individual DRAMs. The ID codes are used to index stored fail maps taken from the DRAMs prior to their assembly onto a SIMM. After all failing locations of all of the DRAMs located on a single SIMM are determined, the SIMM is then programmed to re-route these locations to auxiliary memory located on the SIMM.