Paul William Rutkowski

US Patent:

7005873, Feb 28, 2006

Filed:

Dec 31, 2002

Appl. No.:

10/335540

Inventors:

Laurence Reeves - Crowthorne, GB
Paul W. Rutkowski - Bridgewater NJ, US
Jing Wu - North Brunswick NJ, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

G01R 31/26

US Classification:

324765, 324763, 714733

Abstract:

A built-in, self-test (BIST) network employs a hierarchy of Universal BIST schedulers (UBSs) for scheduling and coordinating testing of elements, such as regular structure BISTed (RSB) elements and random logic BISTed (RLB) elements. Individual UBSs are preferably positioned in local areas, or sections, of an integrated circuit for testing of RSB and RLB elements within the local area. Testing of RSB and RLB elements within the local area allows the BIST network to minimize effects of delay and clock skew by employing relatively short interconnect routing between BISTed elements. Each of the individual UBSs are, in turn, controlled by a master UBS (MUBS) via simplified timing of control signals. The MUBS also may interface with an external testing device that initiates BISTed testing.

US Patent:

20040199838, Oct 7, 2004

Filed:

Mar 19, 2003

Appl. No.:

10/392011

Inventors:

Paul Rutkowski - Bridgewater NJ, US
Larry Wall - Fogelsville PA, US

International Classification:

H03K019/00
G01R031/28

US Classification:

714/724000

Abstract:

An integrated circuit or other electronic circuitry is tested by arranging device pins into multiple-pin groups, and permitting the device pins of the group to share a single tester channel of a piece of test equipment. More particularly, a group comprising a plurality of device pins of the electronic circuitry is designated, and assigned to one of a plurality of tester channels in the test equipment. A test may then be performed on the electronic circuitry, via the assigned tester channel, utilizing at least a subset of the device pins in the designated multiple-pin group. Advantageously, the invention allows high pin count integrated circuits to be tested using inexpensive test equipment platforms.

US Patent:

51877120, Feb 16, 1993

Filed:

Feb 26, 1990

Appl. No.:

7/484336

Inventors:

John A. Malleo-Roach - Lambertville NJ
Paul W. Rutkowski - Morris Plains NJ
Eleanor Wu - Princeton NJ

Assignee:

AT&T Bell Laboratories - Murray Hill NJ

International Classification:

G01R 3128

US Classification:

371 221

Abstract:

Psuedo-exhaustive self-testing of an electronic circuit (10), containing groups of combinational elements (14. sub. 1, 14. sub. 2, 14. sub. 3. . . 14. sub. n), is accomplished by first partitioning the groups of combinational elements into sub-cones having no more than w imputs each by designating appropriate nodes ("test points") in each cone as the output of a sub-cone. A set of test vectors {a. sub. 1, a. sub. 2. . . a. sub. w, b. sub. 1, b. sub. 2. . . b. sub. w } is then generated (via an internal generator 74) such that when the vectors are applied to the sub-cones (14. sub. 1. sbsb. a, 14. sub. 1. sbsb. b. . . . 14. sub. i. sbsb. j), each sub-cone will be exhaustively tested. Each of the inputs of the sub-cones is assigned to receive a vector such that the vectors received at the inputs are linearly independent. The subset of vectors is applied through each of a plurality of pseudo-exhaustive self-test (PEST) flip-flop circuits (88) and through the test points to test the circuit.

US Patent:

59789476, Nov 2, 1999

Filed:

Oct 7, 1997

Appl. No.:

8/944617

Inventors:

Ilyoung Kim - Plainsboro NJ
Paul William Rutkowski - Bridgewater NJ
Yervant Zorian - Santa Clara County CA

Assignee:

Lucent Technologies Inc. - Murray Hill NJ

International Classification:

G01R 3128

US Classification:

714733

Abstract:

This invention relates to a token passing network, called a Universal BIST Scheduler (UBS), and a method for scheduling BISTed memory elements based on: executing BIST in multiple stages in order to optimize the efficiency of continuous processing and to apply a single waiting period to multiple SBRIC. sub. -- RSs where, for example, BIST includes retention testing; dividing resource controllers or SBRIC. sub. -- RSs corresponding to one or more RSB elements into a matrix such that each SBRIC. sub. -- RS executes the BIST of its memory elements concurrently and/or successively depending on the SBRIC. sub. -- RS's position in the matrix; and passing a token to initiate processing of a set of SBRIC. sub. -- RSs in the matrix through a level signal rather than a pulse signal in order to ensure that the signal is not lost.

US Patent:

54901510, Feb 6, 1996

Filed:

Jul 26, 1993

Appl. No.:

8/096286

Inventors:

William E. Feger - Macungie PA
Paul W. Rutkowski - Morris Plains NJ

Assignee:

AT&T Corp. - Murray Hill NJ

International Classification:

G01R 3128

US Classification:

371 223

Abstract:

A Boundary-Scan cell (12') for facilitating testing of an electronic device (10), includes a system flip-flop (30') interposed between an output buffer (18) of the device and an internal logic block (14) which drives the buffer. The system flip-flop has asynchronous clear and preset capability which allows the flip-flop to be cleared or preset as necessary so that its output bit reflects a bit previously latched in the Boundary-Scan cell during testing. During non-testing intervals, the preset and clear capability of the system flip-flop (30') is disabled to allow the flip-flop to pass a bit between the internal logic of the device and the output buffer without undue propagation delays.

US Patent:

62371231, May 22, 2001

Filed:

Oct 7, 1997

Appl. No.:

8/944618

Inventors:

Ilyoung Kim - Plainsboro NJ
Paul William Rutkowski - Bridgewater NJ
Yervant Zorian - Santa Clara County CA

Assignee:

Lucent Technologies Inc. - Murray Hill NJ

International Classification:

G06F 1100

US Classification:

714733

Abstract:

This invention relates to a token passing network, called a Universal BIST Scheduler (UBS), and a method for scheduling BISTed memory elements based on: executing BIST in multiple stages in order to optimize the efficiency of continuous processing and to apply a single waiting period to multiple SBRIC_RSs where, for example, BIST includes retention testing; dividing resource controllers or SBRIC_RSs corresponding to one or more RSB elements into a matrix such that each SBRIC_RS executes the BIST of its memory elements concurrently and/or successively depending on the SBRIC_RS's position in the matrix; and passing a token to initiate processing of a set of SBRIC_RSs in the matrix through a level signal rather than a pulse signal in order to ensure that the signal is not lost.

US Patent:

56235038, Apr 22, 1997

Filed:

Jul 2, 1996

Appl. No.:

8/668502

Inventors:

Paul W. Rutkowski - Bridgewater NJ

Assignee:

Lucent Technologies Inc. - Murray Hill NJ

International Classification:

G01R 3128

US Classification:

371 223

Abstract:

Partial-Scan testing of an integrated circuit (10) having a Boundary-Scan architecture (18) is accomplished by way of a Partial-Scan controller (36) contained within the integrated circuit. In response to control signals generated by Boundary-Scan architecture (18), the Partial-Scan controller (36) generates a set of Partial-Scan control signals for causing the integrated circuit to accomplish Partial-Scan testing. In this way, the Partial-Scan control signals necessary to accomplish Partial-Scan testing are generated internally, rather than requiring a separate set of input pins to receive the Partial-Scan control signals from an external source.

US Patent:

54576970, Oct 10, 1995

Filed:

Aug 26, 1992

Appl. No.:

7/935322

Inventors:

John A. Malleo-Roach - Lambertville NJ
Paul W. Rutkowski - Morris Plains NJ
Eleanor Wu - Princeton NJ

Assignee:

AT&T IPM Corp. - Coral Gables FL

International Classification:

G01R 313183
G01R 313185

US Classification:

371 223

Abstract:

Pseudo-exhaustive self-testing of an electronic circuit (10), containing groups of combinational elements (14. sub. 1,14. sub. 2, 14. sub. 3. . . 14. sub. n), is accomplished by first partitioning the groups of combinational elements into sub-cones having no more than w inputs each by designating appropriate nodes ("test points") in each cone as the output of a sub-cone. A set of test vectors {a. sub. 1, a. sub. 2. . . a. sub. w, b. sub. 1, b. sub. 2. . . b. sub. w } is then generated (via an internal generator 74) such that when the vectors are applied to the sub-cones (14. sub. 1. sbsb. a, 14. sub. 1. sbsb. b. . . . 14. sub. i. sbsb. j), each sub-cone will be exhaustively tested. Each of the inputs of the sub-cones is assigned to receive a vector such that the vectors received at the inputs are linearly independent. The subset of vectors is applied through each of a plurality of pseudo-exhaustive self-test (PEST) flip-flop circuits (88) and through the test points to test the circuit. The PEST flip-flop circuits 88 also serve to advantageously compact and observe the response data produced by each sub-cone (14. sub. i. sbsb.