Paul M Rutkowski

US Patent:

54901510, Feb 6, 1996

Filed:

Jul 26, 1993

Appl. No.:

8/096286

Inventors:

William E. Feger - Macungie PA
Paul W. Rutkowski - Morris Plains NJ

Assignee:

AT&T Corp. - Murray Hill NJ

International Classification:

G01R 3128

US Classification:

371 223

Abstract:

A Boundary-Scan cell (12') for facilitating testing of an electronic device (10), includes a system flip-flop (30') interposed between an output buffer (18) of the device and an internal logic block (14) which drives the buffer. The system flip-flop has asynchronous clear and preset capability which allows the flip-flop to be cleared or preset as necessary so that its output bit reflects a bit previously latched in the Boundary-Scan cell during testing. During non-testing intervals, the preset and clear capability of the system flip-flop (30') is disabled to allow the flip-flop to pass a bit between the internal logic of the device and the output buffer without undue propagation delays.