Paul J Tsang

US Patent:

52850994, Feb 8, 1994

Filed:

Dec 15, 1992

Appl. No.:

7/990679

Inventors:

Roy A. Carruthers - Stormville NY
Fernand J. Dorleans - Wappinger Falls NY
John A. Fitzsimmons - Poughkeepsie NY
Richard Flitsch - Poughkeepsie NY
James A. Jubinsky - Clinton Corners NY
Gerald R. Larsen - Cornwall NY
Geraldine C. Schwartz - Poughkeepsie NY
Paul J. Tsang - Poughkeepsie NY
Robert W. Zielinski - Wappinger Falls NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2702
H01L
H01L 2946

US Classification:

257529

Abstract:

A SiCr microfuse, deletable either by electrical voltage pulses or by laser pulses, for rerouting the various components in an integrated circuit, as where redundancy in array structures is implemented, and the method of fabricating same, at any wiring level of the chip, by utilizing a direct resist masking of the SiCr fuse layer to eliminate problems of mask damage and residual metal adjacent the fuse.

US Patent:

53745906, Dec 20, 1994

Filed:

Apr 28, 1993

Appl. No.:

8/053282

Inventors:

Kerry L. Batdorf - Poughkeepsie NY
Richard A. Gilmour - Colchester VT
Paul Tsang - Poughkeepsie NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21268

US Classification:

437173

Abstract:

A method of fabricating a microfuse, deletable by laser pulses utilizes laser pulses of a predetermined spot diameter and beam alignment accuracy. A fusible link forming a portion of the microfuse is defined such that its length is at least equal to the sum of the laser spot diameter and the beam alignment accuracy and its width is no greater than half the laser spot diameter. A method of deleting the microfuse by laser pulses is provided where the microfuse has a predetermined composition, length and width having an axis bisecting the width and parallel to the length and is covered with a passivation layer at least 3. mu. m thick. The method includes adjusting the diameter of the beam of laser light (i) to at least a minimum diameter of W+. DELTA. P. sub. w, where W equals the width of the microfuse fuse link and. DELTA. P. sub. w equals the accuracy of the beam in the direction of W and (ii) to no more than a maximum diameter of L+. DELTA. P. sub.

US Patent:

44920083, Jan 8, 1985

Filed:

Aug 4, 1983

Appl. No.:

6/520366

Inventors:

Narasipur G. Anantha - Hopewell Junction NY
Tak H. Ning - Yorktown Heights NY
Paul J. Tsang - Poughkeepsie NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2708
H01L 2176

US Classification:

29571

Abstract:

A high performance lateral transistor may be fabricated by first providing a monocrystalline semiconductor body having a principal surface and where the desired transistor is a PNP transistor, a buried N+ region with an N+ reach-through connecting the buried region to said principal surface. The collector region of the transistor is formed into the surface by blanket diffusing P type impurities into the desired region. An insulating layer is formed upon the top surface of the semiconductor body. An opening is made in the insulating layer where the groove or channel-emitter contact is desired. An etching of a substantially vertical walled groove into the monocrystalline semiconductor body using the patterned insulating layer as the etching mask. An N base diffusion is carried out to produce as N region around the periphery of the opening in the body. Oxygen is then ion implanted into the bottom of the groove to form a silicon dioxide region at the bottom of the groove.

US Patent:

43666132, Jan 4, 1983

Filed:

Dec 17, 1980

Appl. No.:

6/217497

Inventors:

Seiki Ogura - Hopewell Junction NY
Paul J. Tsang - Poughkeepsie NY

Assignee:

IBM Corporation - Armonk NY

International Classification:

H01L 2126

US Classification:

29571

Abstract:

A method of manufacturing LDD MOS FET RAM capable of delineating short (less than 1 micrometer) lightly doped drain regions. An N. sup. - implant is effected between gate electrodes and field oxide insulators, before the N. sup. + implant. An insulator layer is then deposited also prior to N. sup. + ion implantation. Reactive ion etching of the layer leaves narrow dimensioned insulator regions adjacent the gate electrode which serves to protect portions of the N. sup. - impurity region during the subsequent N. sup. + implant. These protected regions are the lightly doped source/drain regions.

US Patent:

49086910, Mar 13, 1990

Filed:

Oct 9, 1987

Appl. No.:

7/106210

Inventors:

Victor J. Silvestri - Hopewell Junction NY
Paul J. Tsang - Poughkeepsie NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2912

US Classification:

357 49

Abstract:

A novel method of employing selective epitaxial growth, in which interdevice isolation is intrinsically formed. Problems stemming from formation of all active device elements within selective epitaxial growth regions are addressed. Additionally, there is shown a novel transistor array formed according to the method of the invention.

US Patent:

45465363, Oct 15, 1985

Filed:

Aug 4, 1983

Appl. No.:

6/520365

Inventors:

Narasipur G. Anantha - Hopewell Junction NY
Jacob Riseman - Poughkeepsie NY
Paul J. Tsang - Poughkeepsie NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2122
H01L 2708
H01L 2176

US Classification:

29571

Abstract:

The lateral transistor is described which has both its base width and the emitter region of the transistor minimized. This minimization of the elements of the lateral transistor gives high performance. The lateral transistor which may be typically PNP transistor is formed in a monocrystalline semiconductor body having a buried N+ region within the body. A P type emitter region is located in the body. An N type base region is located around the side periphery of the emitter region. A P type collector region is located in the body surrounding the periphery of the base region. A first P+ polycrystalline silicon layer acting as an emitter contact for the emitter region is in physical and electrical contact with the emitter region and acts as its electrical contact. A second P+ polycrystalline silicon layer is located on the surface of the body to make physical and electrical contact with the collector region. A vertical insulator layer on the edge of the second polycrystalline silicon layer isolates the two polycrystalline silicon layers from one another.

US Patent:

39986748, Dec 21, 1976

Filed:

Nov 24, 1975

Appl. No.:

5/634571

Inventors:

Donald P. Cameron - Poughkeepsie NY
Paul J. Tsang - Poughkeepsie NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2176
H01L 2120

US Classification:

148175

Abstract:

An improved method for forming a recessed thermal SiO. sub. 2 isolation region in a monocrystalline silicon semiconductor body having a major surface lying in a (100) plane as defined by the Miller indices by forming an etch resistant and oxidation resistant masking layer on the major surface of the body, forming at least one rectilinear annular opening in the masking layer, the opening being oriented with the sides parallel to the [100] directions on the major surface, removing a portion of the exposed body by anisotropic chemical etching, and oxidizing the resultant exposed portions of the body until the surface of the resultant SiO. sub. 2 and major surface are substantially coplanar. A semiconductor device including a silicon substrate of a first conductivity, the major surface being in the (100) plane, an epitaxial silicon layer on the substrate, a lateral PN junction in the substrate, at least one annular rectangular shaped recessed SiO. sub. 2 region in the epitaxial layer extending inwardly to the PN junction, the annular region being oriented with the sides parallel to the [100] direction on the major surface.

US Patent:

49607170, Oct 2, 1990

Filed:

Aug 19, 1988

Appl. No.:

7/234058

Inventors:

Victor J. Silvestri - Hopewell Junction NY
Paul J. Tsang - Poughkeepsie NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21265

US Classification:

437 33

Abstract:

A novel method of employing selective epitaxial growth, in which interdevice isolation is intrinsically formed. Problems stemming from formation of all active device elements within selective epitaxial growth regions are addressed. Additionally, there is shown a novel transistor array formed according to the method of the invention.