Paul J Ward

US Patent:

7219337, May 15, 2007

Filed:

Mar 6, 2003

Appl. No.:

10/382598

Inventors:

William J. Cannon - Centerville OH, US
Eric W. Zwirner - Dayton OH, US
Timothy R. Hoerig - Beavercreek OH, US
Paul D. Ward - Centerville OH, US

Assignee:

Northrop Grumman Corporation - Los Angeles CA

International Classification:

G06F 9/45

US Classification:

717138, 717151

Abstract:

A method and system for emulating instructions of legacy microprocessors which execute a compiled high-ordered language, such as C/C++, in which the compiled code is structured such that data and instructions segments are segregated. In order to improve the real-time performance of the system, legacy instructions are directly mapped to equivalent instructions of the host processor where possible. Additional techniques may optionally be employed to further increase the real-time performance of the system. By utilizing the direct mapping of the legacy instructions to host instructions, the emulation system in accordance with the present invention provides increased real-time performance for relatively modern RISC microprocessors.

US Patent:

62724533, Aug 7, 2001

Filed:

Nov 30, 1999

Appl. No.:

9/451156

Inventors:

Timothy R. Hoerig - Beavercreek OH
William J. Cannon - Centerville OH
David K. Remnant - Dayton OH
Paul D. Ward - Centerville OH

Assignee:

TRW Inc. - Redondo Beach CA

International Classification:

G06F 9455

US Classification:

703 27

Abstract:

A method and apparatus for emulating instructions of a microprocessor ("legacy instructions") with an incompatible instruction set which provides increased throughput relative to known emulation systems. In particular, each word of legacy memory is translated into an opcode/operand field and a dual function vector/tag field. The vector field represent addresses to legacy instruction emulation routines. The tag field is indexed to table of "thunk" objects, which can be used for various purposes. Such purposes include a disabling part of the legacy software, augmenting the legacy software with native software, and gathering execution statistics without modifying the legacy software.

US Patent:

60414022, Mar 21, 2000

Filed:

Jan 5, 1998

Appl. No.:

9/002960

Inventors:

William J. Cannon - Centerville OH
David K. Remnant - Dayton OH
Paul D. Ward - Franklin OH
Timothy R. Hoerig - Beavercreek OH

Assignee:

TRW Inc. - Redondo Beach CA

International Classification:

G06F 930

US Classification:

712200

Abstract:

A method and apparatus for emulating instructions of one microprocessor ("legacy instructions") with instructions of another microprocessor with an incompatible instruction set which provides increased throughput relative to known emulation systems. In particular, the legacy instructions are translated into direct vectors to software routines for each legacy instruction. Rather than fetching the legacy instruction and interpreting the instruction in software, the emulation system and method in accordance with the present invention fetches the direct vectors to the software routines which emulate the legacy instructions. The legacy instructions can either be translated by way of software when the legacy memory is loaded or modified, or by way of hardware when legacy memory is accessed. By fetching the direct vectors, the need for software-based look-up tables for interpreting the legacy instructions is obviated. As such, the probability of cache misses is greatly reduced which increases the throughput of the system.