Paul B Wiley

US Patent:

6654646, Nov 25, 2003

Filed:

Dec 13, 2000

Appl. No.:

09/735967

Inventors:

Thomas Earl Bowers - Warrenville IL
Robert Joseph Gamoke - Batavia IL
Glen D. Rocque - Aurora IL
Paul Ronald Wiley - Naperville IL

Assignee:

Lucent Technologies Inc. - Murray Hill NJ

International Classification:

G05B 1918

US Classification:

700 5, 700 1, 700 2, 700 3, 700 4, 711100, 711101, 711214, 711200, 711220, 712 14, 712 25, 712 27, 712200, 712204

Abstract:

A processing or control system having arrangements for separately and simultaneously generating instruction addresses and data addresses having two bus systems for accessing instruction and data storage, and having a single address range for both instructions and data. The boundary between the instruction range and the data range can be varied and placed under the control of the processor according to the needs of the particular application being processed. Some or all of the blocks of storage can access either the instruction bus or the data bus system, and the selection is made under the control of a control register within the processor. Advantageously, applications which require a larger amount of instruction storage, this can be provided; for applications which require a larger amount of data storage, that can be provided also; both are limited only by the total amount of storage available.

US Patent:

20020073295, Jun 13, 2002

Filed:

Dec 13, 2000

Appl. No.:

09/735966

Inventors:

Thomas Bowers - Warrenville IL, US
Robert Gamoke - Batavia IL, US
Glen Rocque - Aurora IL, US
Paul Wiley - Naperville IL, US

International Classification:

G06F012/02

US Classification:

711/200000, 711/214000, 711/220000

Abstract:

In a data processing or control system having arrangements for separately and simultaneously generating instruction addresses and data addresses, having two bus systems for accessing instruction and data storage, and having a single address range for both instructions and data, an arrangement for extending a range of addressable storage beyond the basic range allowed by the instruction codes. The processor is equipped to generate a long address, i.e., 30-bits, even though the instruction execution means can only generate a 23-bit address. When the processor goes into an alternate mode, the contents of a segment control register are prefixed onto the addresses generated within the processor when a certain class of instructions are executed. In accordance with Applicants' preferred embodiment, the class of instructions which call for prefixing of the addresses generated when the processor is in the alternate mode, is an indication that the addresses being generated within the processor are base instruction range addresses for a data access, or base data access instructions for an instruction fetch. Advantageously, mode control can be accomplished within a single cycle. Advantageously, this arrangement allows for accessing memory and a segment control, and under base address control, without unduly limiting the range of the range of operations that can be performed from memory in the base range or the range controlled by the segment controller.

US Patent:

44751893, Oct 2, 1984

Filed:

May 27, 1982

Appl. No.:

6/382602

Inventors:

Diane E. Herr - Warrenville IL
Reinhard Metz - Oswego IL
Laddie E. Suk - Readington NJ
Paul R. Wiley - Naperville IL
David F. Winchell - Glen Ellen IL

Assignee:

AT&T Bell Laboratories - Murray Hill NJ

International Classification:

H04J 312
H04M 356

US Classification:

370 62

Abstract:

A network services complex having an audio conference bridge, a data conference bridge, a tone receiver and a data store announcement system is disclosed. The complex is connected to a telephone network via a host toll switching center. Customers dialing over the network using a keyset can selectively establish audio-only, data-only and combined audio/data conferences. Announcements from the data store prompt the customer in the use of the arrangement and request the user to reenter information when the customer makes an error. Should the customer make too many errors, an operator is summoned.

US Patent:

40125980, Mar 15, 1977

Filed:

Jan 14, 1976

Appl. No.:

5/649045

Inventors:

Paul Ronald Wiley - Naperville IL

Assignee:

Bell Telephone Laboratories, Incorporated - Murray Hill NJ

International Classification:

H04L 708

US Classification:

178 691

Abstract:

A receiver is disclosed which operates for synchronously receiving pulses of a serial stream without synchronizing the receiver clock to the clock at a transmitting site. Circuitry is provided for generating multiple delayed pulse signals in response to each incoming pulse and for sampling and maintaining a sequence of the most recent samples of the pulse signals. Decoding logic detects state transitions within the sequence, the location therein being indicative of the phase of the pulses relative to the clock signals. The decoding logic operates other circuitry for tracking the phase of the pulses as it drifts. The phase tracking circuitry enables the selection of ones of the samples which are synchronized, or in pulse durational phase, with the receiver clock for reconstructing the incoming pulse stream.