Paul A Wilkinson

US Patent:

57650110, Jun 9, 1998

Filed:

Apr 26, 1994

Appl. No.:

8/233210

Inventors:

Paul Amba Wilkinson - Apalachin NY
James Warren Dieffenderfer - Owego NY
Peter Michael Kogge - Endicott NY
Nicholas Jerome Schoonover - Tioga Center NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1580

US Classification:

3958002

Abstract:

A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a single chip have their own associated processing element, significant memory, and I/O and are interconnected with a hypercube based, but modified, topology. These nodes are then interconnected, either by a hypercube, modified hypercube, or ring, or ring within ring network topology. Conventional microprocessor MMPs consume pins and time going to memory. The new architecture merges processor and memory with multiple PMEs (eight 16 bit processors with 32K and I/O) in DRAM and has no memory access delays and uses all the pins for networking. The chip can be a single node of a fine-grained parallel processor. Each chip will have eight 16 bit processors, each processor providing 5 MIPs performance.

US Patent:

56301626, May 13, 1997

Filed:

Apr 27, 1995

Appl. No.:

8/430708

Inventors:

Paul A. Wilkinson - Apalachin NY
Peter M. Kogge - Endicott NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1516

US Classification:

395800

Abstract:

A parallel processor array of the SIMD or MIMD type requires a highly organized communication network for communication between processing elements (PEs). For a communication network a dotted network structure is created which reduces the magnitude of the the networking implementation using a link with two vertical paths and two horizontal paths for a single link, denominated H-DOT. A significant result of the H-DOT network configuration is that it applies to several topologies, and furthermore, the array of processors can generally be extended in size and in additional dimensions while retaining the basic two port array processing element. Both synchronous and routed control can be included. Routing algorithm routines are discussed. The network configuration can be used in massively parallel processors or other smaller array processors which can implement SIMD and MIMD processes.

US Patent:

57650152, Jun 9, 1998

Filed:

Jun 1, 1995

Appl. No.:

8/458859

Inventors:

Paul Amba Wilkinson - Apalachin NY
Thomas Norman Barker - Vestal NY
James Warren Dieffenderfer - Owego NY
Peter Michael Kogge - Endicott NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1580

US Classification:

39580022

Abstract:

In arrays of processors, especially linear arrays, it is important to be able to communicate to adjacent neighbors (en masse). That is, each element of the array can communicate with its neighbor on the left simultaneously. In addition, the array processor is provided with the ability for selected elements of the array, picket processing elements, to simultaneously communicate with other elements that are further away in one dimension than the nearest neighbor in one transfer cycle. This is accomplished by causing intermediate elements to become transparent in the communication paths, thus allowing data to "slide" through intermediate nodes to the destination node. This system can be used in the implementation of fault tolerance in the array of elements.

US Patent:

58092927, Sep 15, 1998

Filed:

Jun 1, 1995

Appl. No.:

8/460515

Inventors:

Paul Amba Wilkinson - Apalachin NY
James Warren Dieffenderfer - Owego NY
Peter Michael Kogge - Endicott NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1516

US Classification:

395563

Abstract:

A floating point system and method according to a format that includes a sign bit, an exponent part having a plurality of bits, and a fraction part having a plurality of multi-bit blocks, wherein floating point operation is based on block shifts of the fraction part, with each shift of one block associated with an increment or decrement of the exponent part by one count. This format illustrated is implemented as a format suitable for the accuracy greater than the IEEE 32-bit floating-point format, and is intended to be implemented in machines having byte-wide (8 bit) data streams. The preferred format consists of a sign bit, 7 exponent bits and 4 fraction bytes of eight bits for a total of 40 bits. This format and implementation allows floating-point commands to be executed in a fixed small number of cycles, thus advancing the capabilities of doing floating-point arithmetic on a SIMD machine. The floating-point implementation is adaptable to multiprocessor parallel array processor computing systems and for parallel array processing with a simplified architecture adaptable to chip implementation.

US Patent:

58420312, Nov 24, 1998

Filed:

Jun 6, 1995

Appl. No.:

8/468045

Inventors:

Thomas Norman Barker - Vestal NY
Clive Allan Collins - Poughkeepsie NY
Michael Charles Dapp - Endwell NY
James Warren Dieffenderfer - Owego NY
Donald George Grice - Kingston NY
Peter Michael Kogge - Endicott NY
David Christoper Kuchinski - Owego NY
Billy Jack Knowles - Kingston NY
Donald Michael Lesmeister - Vestal NY
Richard Ernest Miles - Apalachin NY
Richard Edward Nier - Apalachin NY
Eric Eugene Retter - Warren Center PA
Robert Reist Richardson - Vestal NY
David Bruce Rolfe - West Hurley NY
Nicholas Jerome Schoonover - Tioga Center NY
Vincent John Smoral - Endwell NY
James Robert Stupp - Endwell NY
Paul Amba Wilkinson - Apalachin NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1580

US Classification:

395800

Abstract:

A computer system having a plurality of processors and memory including a plurality of scalable nodes having multiple like processor memory elements. Each of the processor memory elements has a plurality of communication paths for communication within a node to other like processor memory elements within the node. Each of the processor memory elements also has a communication path for communication external to the node to another like scalable node of the computer system.

US Patent:

57650128, Jun 9, 1998

Filed:

Aug 18, 1994

Appl. No.:

8/292943

Inventors:

Paul Amba Wilkinson - Apalachin NY
Thomas Norman Barker - Vestal NY
James Warren Dieffenderfer - Owego NY
Peter Michael Kogge - Endicott NY
Donald Michael Lesmeister - Vestal NY
Robert Reist Richardson - Vestal NY
Vincent John Smoral - Endwell NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1580

US Classification:

39580016

Abstract:

A controller for a SIMD processor array that can execute instructions within each processing element is described. This three stage hierarchical controller executes instructions at the function, routine, and micro-level, to maximize the effectiveness of processing within the array elements themselves. The routine sequencer is hardwired to perform looping and flow control operations using DO/WHILE, IF/THEN/ELSE, and GO-SUB constructs. A pipeline is provided to maintain a steady flow of commands to the array, and means is provided to monitor command execution progress and to provide feedback of progress to the stages of the controller.

US Patent:

58059156, Sep 8, 1998

Filed:

Jun 27, 1997

Appl. No.:

8/883806

Inventors:

Paul Amba Wilkinson - Apalachin NY
James Warren Dieffenderfer - Owego NY
Peter Michael Kogge - Endicott NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1516
G06F 1580

US Classification:

3958002

Abstract:

A conventional SIMD processor array architecture's functions are amplified by a SIMIMD architecture where more programmable flexibility would be useful. Decision making in general and specifically classification where decision trees are common, is a problem eased by SIMIMD. A SIMD array processor having a plurality of pickets in SIMIMD mode allows each picket to occasionally execute data-dependent instructions that are different from the instructions in other pickets to greatly improve execution efficiency in decision making areas. Every element in A SIMD array of processors receives a stream of commands from the array controller. Here several mechanisms allow an array machine with individual processing elements, called pickets, to interpret some of the SIMD commands in their own unique way, giving each picket a degree of local autonomy. A resulting capability allows the pickets to execute instructions in a mode called SIMIMD. Another resulting capability boosts the performance of executing floating-point instructions significantly.

US Patent:

57548714, May 19, 1998

Filed:

Jun 7, 1995

Appl. No.:

8/480893

Inventors:

Paul Amba Wilkinson - Apalachin NY
James Warren Dieffenderfer - Owego NY
Peter Michael Kogge - Endicott NY
Nicholas Jerome Schoonover - Tioga Center NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1580

US Classification:

395800

Abstract:

A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a single chip have their own associated processing element, significant memory, and I/O and are interconnected with a hypercube based, but modified, topology. These nodes are then interconnected, either by a hypercube, modified hypercube, ring, or ring within ring network topology. Conventional microprocessor MMPs consume pins and time going to memory. The new architecture merges processor and memory with multiple PMEs (eight 16 bit processors with 32K and I/O) in DRAM and has no memory access delays and uses all the pins for networking. The chip can be a single node of a fine-grained parallel processor. Each chip will have eight 16 bit processors, each processor providing 5 MIPs performance.